HP puts clear blue water between McKinley, Itanic Mk1

IDF When we spoke to Jim Carlson, HP's IA-64 chief on Friday, we also got treated to an all-star line up of engineers from its chipset division. Andrew Wheeler, who heads up the R&D at the chipset division, and Jim Brokish talked us through the new chipset design.

Real kit based on the zx1 (for Brits of a certain age, it's sooo hard not to slip an '8' between the x and the 1, there) won't appear until the summer. But the zx1 is the first detailed McKinley chipset to streak into public view.

The zx1 has an integrated I/O controller (the zx1 ioa) that handles AGP-4X, PCI and PCI-X. The memory controller (zx1 sme) talks to 200Mhz DDR, with a 4.3 GB/s throughout. There are eight I/O channels. The fourway version of the chipset uses four of these for two PCI-X 133 buses, and the remainder for PCI-X 66. The two-way version opts for an AGP bus in place of one of the PCI-X buses. The single-processor chipset divvies six channel between the AGP bus (two), the PCI-X 133 (two) and two PCI-66 buses. HP claims a slightly lower throughput of 3 GB/s for the single processor version.

"Only data transfers from the processor cache to I/O appear on the processor bus," says Andrew. "That minimizes the traffic: all other DMA transfers are kept off the bus."

"Some chipsets take advantage of DMA off the bus, but we're sensitive to performance and cost. We attach the DIMM buses directly to the chipset."

"Our product strategy is to run through the low-end RISC and then the midrange, then high-end," explains Carlson. So zx1 has been built with price performance as an important consideration.

But HP still expects trials to continue for some time.

"We expect interest from the public sector - particularly in simulation and modeling. And for Linux clusters. For another year people will say 'I want to put this in a pilot that mimics a business process. Or add some to existing web server farms'".

HP says it's already taken an order for the zx1-based McKinleys, but can't say who. ®