Letter from architect A scientist who has taken time out to read Intel's IA-64 material is concluding that the processor may well be a pup. The boffin, who has supplied his name and address to The Register, is concluding that Intel may have a real problem persuading the world+dog that its IA-64 architecture is a goer. He said: "Like many other computer architecture techno-junkies I downloaded Intel's IA-64 instruction set document. As a scientist, I'm fascinated; the most informative experiments are those that fail to produce the predicted results. "But from an engineering point of view it's pretty bad. My fairly confident prediction: instead of Merced being a poor start which will be triumphantly reversed by later models, IA-64 CPUs will remain slower, hotter and much harder to build than CPUs using simpler instruction sets. Only if that competition evaporates completely, and Intel still feel the need to move on from x86, will IA-64 succeed. Oddly, nobody seems to be saying that in public. "IA-64 is a bizarre portmanteau of ideas - some, individually, quite good - with little sense of overall direction. The design committee obviously found it easier to add ideas than to keep them out. "Its complexity has delayed it for at least a year. Even Microprocessor Report (big Intel fans) suggest the new features will deliver no better than a 20% performance increase over a simple (eg Alpha/MIPS) RISC; but you need at least 40% to justify an extra year in development. "History suggests that the compiler support IA-64 performance depends on won't happen. In any case CPU application loads are increasingly going to be interpreted code - even if its not Java - and it would be hard to imagine any CPU more hostile to 'just-in-time' and other interpretation tricks. "Particularly bizarre are several features from the "tried that, didn't work" category, including: only one addressing mode for load/store (AM29K); hardware register windows (Sparc, Pyramid). "And there's the dog that didn't bark. All current, competitive, high-performance processors are register-renaming out-of-order (RR/OOO) machines where the hardware schedules instruction flow. "IA-64 was conceived at a time when the first painful attempts at RR/OOO had left many shell-shocked project casualties determined that there must be a better way. But there wasn't. IA-64, born at the wrong time, is hostile to RR/OOO technology. It nicely replays the late 80's challenge of pipelining the x86 instruction set. "Locally catastrophic is that IA-64's x86 emulation is not in a separate unit (as the Register predicted, and as a wiser architect would have done it) but spread thinly across the whole machine. It seems unlikely that an IA-64 machine will come close to equalling the performance/MHz of Pentium-Pro's many descendants - and that surely is a key feature for success. "PS: If I ran Intel, I'd have a backroom team building an RR/OOO implementation of a simple MIPS/Alpha-style 64-bit RISC instruction set with a (perhaps entirely separate) Pentium-III on the same die, sharing second-level cache and memory. Launching such a thing would be bad for loyal partner HP, but easily justified - amid floods of tears - by the need to rescue those committed to the late and disappointing IA64 CPUs." ®