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DARPA seeks SSITH lords to keep hardware from the Dark Side

'Make chips secure', because nobody's thought of that before

DOor to a bank vault. Photo by Shutterstock

America's Defense Advanced Research Project Agency reckons too many vulnerabilities arise from hardware design errors, so it wants experts and boffins to propose better hardware-level security mechanisms.

Baked-in security is a vexed question, for good reason: recipe slips can also hard-wire vulnerabilities into a chip. For example, Intel's Security Guard Extensions (SGX) is a favourite target for attack boffins crafting proofs-of-concept against the architecture.

Nonetheless, DARPA wants something better than “patch and pray” software security, so on April 21, it's hosting a Proposers Day for its System Security Integrated Through Hardware and Firmware (SSITH – presumably the extra letter is there to avoid getting LucasFilm lawyers' letters).

What it wants is “hardware design tools that provide security against hardware vulnerabilities”, for both Department of Defense and commercial systems.

They want designers to “limit the permitted hardware to states that are assured to be secure”, without sacrificing performance.

Of particular interest in the DARPA program are the seven vulnerability classes known as Common Weakness Enumeration (CWE) applicable to hardware but exploitable through software.

These are permission/privilege errors, buffer errors, resource management, information leakage, numeric errors, cryptographic errors, and code injection vulnerabilities. Together, DARPA reckons hardware bugs of this type represents 40 per cent of currently known attacks.

The program is managed by Linton Salmon of DARPA's Microsystems Technology Office, who in the agency's announcement says software patches to hardware flaws aren't enough.

The SSITH program wants to “remove those hardware vulnerabilities in ways that will disarm a large proportion of today’s software attacks.”

SSITH is a 39-month program covering “development and demonstration of hardware architectures”; and techniques to measure the security of new hardware designs, including tradeoffs in things like performance, power efficiency, and circuit area. ®


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