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Exascale HPC project pours Euro gravy into Mont-Blanc

SoCing it to the ARM-powered nodes

The European Commission's multi-phase, super-dupe-compute project Mont-Blanc is pouring more euro gravy into developing an army of ARM SoC compute nodes.

It has picked Atos's Bull organisation to build an exascale-class compute node using Cavium's Thunder X2 64-bit ARMv8-A server processor SoC (System-on-Chip).

The Mont-Blanc project was started in 2011 and its website says it aims to develop a computer architecture "capable of setting future global HPC standards" and using energy-efficient processors. It has completed two phases, co-ordinated by the Barcelona Supercomputing Center (BSC), and funded by €16m EC cash and €6m from elsewhere.

The EC has funded a third phase, co-ordinated by Atos, to the tune of €7.9m, which is intended to design a high-end HPC platform able to deliver a higher performance/energy ratio. It will cover HW, operating systems, tools and applications, and intends for the compute node to be manufactured at industrial scale.

Atos says the project will leverage the infrastructure of the Bull sequana pre-exascale supercomputer range for network, management, cooling, and power. Atos and Cavium signed an agreement to collaborate on this and made Mont-Blanc an alpha site for ThunderX2.

ThunderX2_graphic

Cavium ThunderX2

Most of the application SW, tools and code libraries for ARM CPUs are focussed on its smartphone usage, and part of Mont-Blanc's aim is to build an HPC SW infrastructure for ARM with tools, code stacks and libraries.

The Mont-Blanc project is run by a consortium which includes Atos, ARM, AVL (Austrian power train developer) and seven academic institutions, including the BSC. A phase 3 test platform using ThunderX2 SoCs should be deployed later this year. ®

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