QLC flash is tricky stuff to make and use, so here's a primer

Readin', writin' and a-bit-matic

Understanding QLC flash can be frustrating

QLC flash primer Quad-level cell (QLC) flash stores 4 bits per NAND cell and is very tricky stuff to use, far trickier than TLC (3 bits/cell) which is harder to user than 2 bits/cell MLC which, you guessed it, is more difficult to use than 1bit/cell SLC. Why is QLC the hardest of all to use?

It is the slowest to read and write and has the shortest endurance, think <100 erase cycles, before it wears out.

Yes, OK, but why?

To help me understand this I had to go back to NAND flash cell basics. Here is my understanding of NAND flash basics 101.

Floating gate NAND cell

A NAND flash cell is typically made with a floating gate transistor design.

Electricity flows through a transistor. There are three wires connecting a transistor to other things: source, drain and gate. Basically electricity can flow from the source to the drain helped by the state of the gate. If the gate is shut electricity flows. If it is open it does not.


Schematic floating gate NAND cell

The state of this floating gate can be changed by a specific process, and once changed stays in that state, i.e. is non-volatile, until it is changed back by a second specific process. It stays in that re-changed state as well.

A transistor used in NAND flash has a second gate, above the floating gate, which is called a control gate. There is an insulating layer between the control and floating gates and a thinner tunnel oxide one between the floating gate and the source and drain areas. This whole structure sits on a substrate which separates the source and drain areas.

When the floating gate is shut electricity can pass between the source and drain and this charged state registers a binary 0. An open or uncharged gate means electricity cannot flow from source to drain and that’s a binary 1. How is the floating gate opened and closed?

Gate opening and closing

The source and drain areas are made of (doped with) n-type silicon which has lots of electrons. The differently doped p-silicon substrate material is deficient in electrons. When a relatively high voltage, say 18V, is applied to the control gate through the wordline, and a lower, ground, voltage is applied to the drain and substrate through the bitline, then a strong electronic field is set up. Electrons flow from source to drain and also some move from the substrate to the floating gate through the tunnel oxide via the Fowler-Nordheim quantum tunnelling effect.

The floating gate is thus charged, meaning it is now closed, as electricity cannot flow from source to drain, and the cell registers a binary 0.

The cell is then said to have a threshold voltage of, for example, 1V or higher.

We reverse this process to erase the cell contents and set it to binary 1 by applying a ground or negative voltage to the control gate and a high voltage to the substrate, ie. 20V. A strong reverse electronic field is set up and electrons now tunnel from the floating fate back into the substrate, as well as flowing from drain to source, and this facilitates future electricity flow between the source and the drain areas.

The cell now has a threshold voltage of, ie. -3V or lower. This threshold voltage change is crucial to NAND cell operation.

Reading and Cell threshold idea

Reading a flash cell involves measuring the flow of electricity between the source and the drain. We need to understand that the voltage threshold above which current will flow between the source and drain varies with the state of the floating gate.

A reference or read-point voltage is applied across the source and drain and the current is tested. If it exists at a high enough level we have a binary 1 and if it does not we have a binary 0. There is a fair amount of error headroom here; we are only looking for enough current to be measured to enable us to declare a current flow state or not.

That is the case for SLC NAND. It is different for multi-level cells. MLC is 2 bits/cell, with TLC being 3 bits/cell and QLC being 4 bits/cell.

Possible binary values for SLC, MLC, TLC and QLC cells:

  • SLC = 0 or 1 - meaning two states and one threshold voltage,
  • MLC = 00, 10, 01, or 11 - four states and so three threshold voltages,
  • TLC = 000, 001, 010, 011, 100, 101, 110, 111 - eight states and thus seven threshold voltages,
  • QLC = 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 - 16 states and so 15 threshold voltages.

Each binary value has a different threshold voltage, with the lowest binary value having the highest voltage, the highest binary value the lowest voltage, and intermediate states having progressively different threshold voltage values.

Thus,for QLC:

  • Binary 0000 has the highest threshold voltage,
  • 0001 has a lower threshold voltage,
  • 0010 has the next lower threshold voltage,
  • 0011 has the next lower threshold voltage,
  • And so on until ...
  • 1111 which has the lowest threshold voltage of all.

The threshold voltage has to be set correctly in the writing process. With QLC cells this means that we set the lowest threshold voltage for binary 1111, a higher one for binary 1110, and so on.

When reading, the threshold voltage tests between groups of states are applied successively, with different threshold voltages being used, and they each take time. With MLC the first threshold voltage test tells you the cell’s binary value is either (00 or 01), or (10 or 11). A further test with a revised threshold voltage is needed to decide between the indicated pair of alternatives.

With TLC, test one gets you 4 possible values (the upper 4 or the lower 4); test two results in 2 possible values; and test three reveals the actual value.

The QLC situation is worse with successive testing going from 16 possible values to 8, then to 4, to 2, and then the final value. It takes the longest time to read.

The cell program and erase time also takes longer as we move from SLC to MLC, then TLC and on to QLC

We haven’t adjusted the overall voltage range used in NAND cell operations as we move from SLC to MLC to TLC and on to QLC, so the precision of the reference voltage setting and the resulting current measurement needs to get finer and finer as the cell bit contents increase.

Gate wear

Each time the cell is re-programmed, in a program-erase cycle, the tunnelling oxide is damaged, and the risk that electrons will leak out of the charged floating gate increases and its effectiveness weakens. Reading cell contents uses a lower voltage which does not damage the tunnelling oxide.

When the gate is damaged then the current measuring (presence vs absence) from application of the read voltage becomes uncertain. The gap between clearly detecting current flow and current non-flow becomes narrower and narrower. Error-correction and detection and digital signal processing techniques can help but, eventually, the measurement is beyond detection and becomes impossible.

Multi-level cells and gate wear

As the gate wears then making the presence/absence decision of current at a particular reference voltage becomes harder and harder. It is harder anyway as we move from SLC through MLC to TLC and QLC. Eventually the acceptable range of error in our measuring process is not enough to overcome the growing ineffectiveness the cell’s state; it is like trying to detect the presence of a vehicle ahead of you on a foggy highway. Eventually the fog becomes too thick for you to be able to see.

This means that with TLC cells and QLC cells, because their tolerances for error in reading are much finer, then their endurance is shorter, with QLC cells having shorter endurance than TLC cells. The thing with 3D NAND is that cell lithography went back from the 19-16nm of the latest 2D planar NAND to 49-40nm and so everything in the cell became larger, including the tunnelling oxide layer, enabling it to last longer, and the cell’s endurance to rise.

What we are now seeing, as 3D NAND fabrication expertise increases, is that QLC NAND can be produced cost-effectively enough so that it could be used in active archive situations where there is a marked skew in favour of reading and a low likelihood of re-writing data, a kind of near-WORM (Write Once Read Many) flash use.

Here is a summary table of NAND cell data:


NAND Cell-type summary data.

As we move from SLC through MLC to TLC and on to QLC we get higher density and lower cost. As we move in the reverse direction we get higher performance and longer life.

This table comes from Anandtech* via Flashdba** and we have added the QLC column using guesstimated data. Until real product arrives we won't have any actual data. ®

*Anandtech's articles on SLC, MLC and TLC flash basics are a great read.

** Flashdba's successive notes on flash basics are also a worthwhile read. Start here.

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