Hand in hand, TSMC, ARM head to 7nm server chip land
Will work together on high-performance data center designs
ARM and TSMC today announced they are working together to make chips featuring 7nm FinFETs a reality. This follows on from their work on 16nm and 10nm FinFETs.
Taiwan-based TSMC describes itself as "the world’s largest dedicated semiconductor foundry," and it churns out chips for the likes of Nvidia, AMD, Qualcomm, Apple, Marvell, and Broadcom. That's a lot of silicon for phones and other handheld devices, the vast majority of which use ARM-designed processor cores.
It's fair to say TSMC and ARM are up to their, er, armpits in mobile chippery.
Yet, the world of phones is not enough: according to their announcement, the pair want their future 7nm parts to push "beyond mobile and into next-generation networks and data centers." They've got their eye on "low-power, high-performance compute system-on-chips," which we've all been waiting for. For years.
Don't forget that ARM designs processor cores, companies license the blueprints and customize them for their own applications, and then outfits like TSMC fabricate the system-on-chips. ARM and TSMC working together doesn't mean ARM is suddenly designing full components: it means ARM is preparing its plans for 7nm to make them more attractive to buyers.
According to people cleverer than this humble hack, TSMC will most likely use multi-patterning lithography at 7nm rather than EUV, which was once heralded as a savior for the semiconductor industry but spluttered to a halt after it had barely left the drawing board.
Right now, chipmakers fire 193nm ultraviolet light through a large design mask, a lens and a fluid – usually purified water – onto silicon wafers coated in photoresist. This is called immersion lithography. The UV laser alters the areas of the photoresist it manages to reach through the gaps in the mask; the exposed sections of the photoresist are then stripped away. This reveals the underlying silicon so that it be etched or layered over with new material. Repeat this over and over with different mask patterns, and you painstakingly craft tiny electronic circuits.
It's extremely tricky using 193nm UV light to construct transistor gates smaller than 22nm, let alone 7nm, due to the physics and material properties involved. EUV was supposed to make the job much simpler, but the backroom boffins can't get it working reliably.
TSMC is not expected to start producing reasonable numbers of 7nm process node chips until 2017. That size is well below the 14nm transistors used in today's processors. Heck, TSMC hasn't even started cranking out 10nm parts yet; those are due to appear later this year. It's hoped that 10nm will be a stepping stone for TSMC to 7nm: if its fabs can nail 10nm, 7nm will follow shortly after.
In July 2015, IBM breathlessly exclaimed it had built 7nm transistor gates, but that was lab work. Intel, the big daddy of semiconductors, has said it will produce 10nm node processors for the first time in the second half of 2017.
So the race is still on: what will come first – Intel's 10nm parts or TSMC's 7nm? And this race is important because, generally speaking, the smaller you can shrink the transistor gates on a chip, the more efficient the chip will be. Power efficiency matters more and more; you want your phone's battery to last longer between charges, and you want your data center to not consume more electricity than a small town. To do that, processors have to work harder on the juice they're given.
You want transistors in your CPU to do two things: switch on and off quickly so they process information rapidly; and leak no current when they're switched off so they don't consume power unnecessarily.
If you're not an electronic engineer, think of the transistor gate as a push-button switch. You have two sides to the switch: the source and the drain. You have a button on top, called the gate, that, when pushed, allows electrons to flow across the switch from the source to the drain, and into the next transistor.
Well-placed source ... diagram of a MOSFET gate (source)
Wire millions of these up and you can build complex decision-making circuits that turn sequences of on and off states – ones and zeroes in binary – into something useful. Below is a simplified 3D model of an ordinary MOSFET...
Source to drain ... Electron flow in a normal transistor gate when switched on (source)
If you want to flip a switch between on and off rapidly, you'll want the gate push button to be fairly sensitive: a small, slight touch should be all that's needed to change the state, rather than a hard thrust to overcome a rusty, clunky mechanism. Of course, if the button's too sensitive, just resting your finger on it in anticipation of the next flip will trigger the switch.
The same goes for transistor gates, to put it simply. When a voltage between the source and gate exceeds a threshold, the transistor starts conducting. It's switched on. If this threshold is too low, then the transistor will let current leak through it even when it shouldn't be conducting at all and should be switched off, thus wasting power. If the threshold is too high, it'll take too long to change to a conducting on state.
Using a smaller transistor means a lower threshold voltage is needed because the gate channel is smaller and switching times reduce. With a lower threshold, a lower supply voltage for the chip is required, which brings down the dynamic power consumption – ie, the amount of power used when gates are active.
However, that lower threshold means you're likely to leak lots of current even when a transistor gate is off, so you'll burn through the battery and kick out too much heat.
As transistors shrink, this leakage problem grows more and more, especially at sub-10nm sizes. A solution is the FinFET design, which has been around in mainstream production for a couple of years now. These lift the source and drain up into a thin fin-like channel and wrap the gate around them. This cocoons the crucial section of the device, prevents leakage in the off-state, and provides more control over the operation of the gate. In other words, you get better power efficiency at lower threshold voltages, and faster running chips. Bingo.
A snazzy FinFET ... electrons flowing from source to drain
Sponsored: Global DDoS threat landscape report