XPoint memory ruminations: Expert says it's not PCM

Flash Memory Summit presentation prompts presumptive postulations

3D XPoint memory wafer

Comment A presentation at the Flash Memory Summit contained speculation about Intel/Micron’s 3D XPoint memory – what it is and how Intel might use it. We’ve tested some of its contents with a knowledgeable industry expert and can cast a little more light, hopefully, on what it is and where it’s going.

The Thursday August 13 presentation was in Session 301-C: "Life Beyond Flash – New Non-Volatile Memory Technologies (New Technologies Track)" and the slide below was used by Dave Eggleston, principal, Intuitive Cognition Consulting, in his “3D Xpoint, MRAM, RRAM: The Future Is Now” slot.

You can’t, by the way, get the slides from the FMS proceedings. Pity. Maybe they’ll be available in a day or two?

Tegile’s Marc Farley was at the presentation and tweeted about what was said.

Marc_2

So Eggleston thinks XPoint is rebranded Phase Change Memory (PCM). The image in the tweet is of a Dave Eggleston slide and looks at possible Intel use of XPoint memory.

Marc Farley tweet

Here’s the slide picture in more detail:

Intel_spec_slide_FMS_2015

Dave Eggleston slide from FMS 2015

I’ve talked to someone who is a knowledgeable industry source and this person thinks that XPoint memory isn’t rebranded PCM. XPoint is using a phase change as a physical process but is a major advance in the design of the underlying cell material and the selector. This is thought to be far ahead of where Toshiba and Samsung are on their development of STT-MRAM (Spin-Transfer Torque Magnetic RAM) or, (in our source’s words) HP's memristor running joke.

XPoint memory is valid technology and hits a key price/density window. It is revolutionary work.

The slide talks about Intel using XPoint in server memory DIMMs. They’ll be timed to coincide with Intel’s Xeon server CPU development called Purley in 2017. Via our expert, we can confirm that as well as the use of a DDR4 bus with a new protocol, there is apparently a lot of tweaking going on with Read’s PCM native latency with the 50-200 ns numbers confirmed.

The write buffer performance is apparently better than the implication on Eggleston’s slide.

The idea of there being 100’s of GBs per DIMM is confirmed, but there is no trouble meeting the 12W power window.

The import of this is that we can expect radically faster servers in 2017, not just from standard Intel CPU refreshes, but from the ability to bring storage to compute and have the multi-cored mills rampage through huge amounts of data in DIMM-mounted 3D XPoint memory modules. Bring it on. ®


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