It's all downhill from here: Avalanche spins STT-RAM
With memory based on the orientation of electrons, scaling is clearly not an issue
Startup Avalanche is sampling an STT-RAM chip offering DRAM/SRAM speed, persistent storage, unlimited endurance and scalability beyond 10nm.
The holy unified memory chip grail is to replace DRAM, SRAM and flash with a single chip tech, offering the benefits of each without the drawbacks. Thus NAND cannot scale down psst 10nm and has endurance issues, while DRAM and SRAM are costly. Avalanche says its STT-RAM chip is not, and draws little power.
STT-RAM (Spin Transfer Torque Random Access Memory) relies on the different spin directions of electrons to signal a binary one or zero.
The Avalanche chip uses proprietary AvRAM technology featuring perpendicular magnetic tunnel junction (pMTJ) cells manufactured on a standard CMOS 300mm process, which it claims is high volume and low cost.
Avalanche says its pMTJ cells have a magnetic "pinned" layer, an MgO barrier layer for high and low-resistance generation, and another magnetic "storage" layer.
The magnetic orientation of the pinned layer is permanently fixed during operation, while that of the storage layer is not. Magnetisation of the storage layer changes its perpendicular direction based on the direction of the electrical current being applied and flowing through the pMTJ cell.
It claims pMTJ requires less real estate than other STT-MRAM implementations, compared with current generation in-plane MTJ cell designs.
The sample chip is built on a 55nm process and is a 32/64Mbit standalone discrete item, with an industry standard SPI interface.
"STT-MRAM has enormous market opportunities due to its speed and endurance as a replacement for volatile memories such as SRAM and DRAM,” said Thomas Coughlin, president of the Coughlin Associates consultancy. “Moving to a non-volatile memory architecture will make significant changes in computer architectures.”
It’s not going to be easy.
Avalanche hopes its use of the SPI interface and manufacturing via standard 300mm CMOS wafers will encourage adoption of its technology. One issue is that the downward NAND scaling limit of 15-10nm cell size – which limits the amount by which future chip capacity (density) can increase by decreasing cell sizes – is being bypassed by 3D technology and its layering of 2D planar NAND.
DRAM is also going the 3D route to bypass a scaling trap. Building chips upwards to increase density is necessary in existing computer designs.
As Coughlin says, the wholesale replacement of DRAM, SRAM and NAND by tech such as STT-RAM will involve huge changes in computer architecture and no-one wants to start out on that road without near-certainty of success.
That will only come from initial and small-scale STT-RAM implementations replacing DRAM, SRAM and NAND and being successful, begetting more and bigger implementations and snowballing – or avalanching in this case.
There are other proposed technologies aimed at replacing DRAM and NAND, such as RRAM with its Memristor variant, carbon nanotube memory, and Phase-Change Memory. All are queuing up at the gateway which could lead to mass-adoption in the future, hoping they will be the winner.
Avalanche says its STT-RAM chip can be used for embedded and standalone use in in storage, mobile, wearable devices and networking equipment. It is also offering its STT-MRAM technology under licence as embedded memory for integrated SoC designs.
Potential OEMs and partners can request more information by contacting Avalanche at email@example.com. ®