Disk is dead, screeches Violin – and here's how it might happen

Death by NAND acronyms: 2D MLC, 3D TLC, 3D QLC

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Analysis And in a flash, disk is dead. Well, actually, not that fast. But flash array flogger Violin Memory is convinced disk is dying in the data centre, killed by a series of NAND acronyms: 2D MLC, 3D TLC and, the final blow, 3D QLC.

Is this view realistic? Even remotely realistic?

It starts from a pair of observations by Violin Memory’s newly appointed SVP for worldwide sales, Said Ouissal:

  • 3D TLC will have the endurance of 2D MLC today
  • 3D QLC will have the endurance of 2D TLC today

Then add to that the generally accepted view that deduplicated 2D MLC flash is killing off the 15,000 rpm disk drive business. One consequence is that disk vendors are focussing more on enterprise capacity disks – meaning 3.5-inch 7,200rpm drives – than enterprise performance disks.

Let’s agree for argument’s sake that these three propositions are true, explain some acronyms, and then start out on a consequences journey.

Most current flash is made with a planar or two-dimensional process, with a single layer of flash cells on a chip.

Flash has endurance problems, because the cells in its blocks wear out with repeated writes. This process is exacerbated by shrinking process geometry and increasing bits per cell. At any process geometry size, 2-bits-per-cell MLC (multi-level cell) flash will have worse endurance than 1-bit SLC (single level cell) flash.

Three bit TLC (triple level cell) will have worse endurance still and 4-bit QLC (quad-level cell) flash will have the worst, meaning lowest, endurance of all.

Flash_Endurance

Relative flash endurance (P/E cycles) at different process sizes and with varying bits/cell values. Thanks to AnandTech for starting numbers

In the chart above, the 5x nm SLC bar has been cut short so that the other bars are more visible. Don’t get fixated on the absolute values: it’s the relative value relationships that matter here and, anyway, controller write reduction and flash over-provisioning affect the absolute Programme/Erase cycle number for any given flash type.

As compensation for lowering endurance, adding bits to flash cells lowers cost/GB. Shrinking the process size also lowers cost/GB, as more cells can be obtained from a standard wafer.

Today, 2D or planar MLC flash is available at 2x (29-20nm) and 1x (19-16nm) process sizes. In anticipation of sub-15nm NAND heading towards complete unreliability due to electron leakage and neighbouring cell influence, it’s now reckoned that 3D (3-dimension) or multi-layer NAND is the way to go to increase flash chip capacity.

Initial 3D chips have reached 32-layers using 4x processes (49-40nm) meaning that, at any particular cell bit level, the endurance is better than the 2x nm class 2D NAND equivalent.

Which phenomenon leads to Ouissal’s two statements above.

He also says that Violin’s flash modules have a 1.1TB capacity now and that future capacity levels of 2.2TB, 4.4TB, and 8.8TB can be expected as each flash generation gives way to the next. He thinks there is one more 2D MLC generation to come before 3D NAND starts being used.

Right, that’s our starting point set out and acronyms defined, and we can start out on a so-what-are-the-consequences journey.


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