Crossbar says it's 'one step' from delivering miracle RRAM

Sneak path current snag cracked: Beyond the NAND scaling wall at last?

Spooky angel doll

Crossbar has jumped a hurdle limiting the readability if its resistive RAM non-volatile memory tech and says commercialisation is getting closer.

Crossbar's resistive RAM (RRAM) tech is a 3D semi-conductor structure promising higher densities and faster access than NAND; closer to the fabled uniform memory that's as fast as DRAM and as non-volatile as flash.

Resistive RAM s one of a number of technologies, including Phase-Change Memory and HP's Memristor concept that are jostling to take-over from NAND - which is hitting a scaling wall preventing it from getting denser or faster, shortening its endurance and weakening its reliability.

This RRAM tech was unveiled when Crossbar came out of stealth in August last year and has had a read problem to deal with; so-called sneak path currents affected the readability of data from cells in the RRAM structure.

In a technical presentation at the recent IEEE International Electron Devices Meeting (IEDM) in San Francisco, CA, the company unveiled its approach to suppressing the sneak path current, a field-assisted superlinear threshold selector device.

Sneak Path concept

Crossbar sneak path diagram

Objective Analysis' Jim Handy attended the meeting and tells us:

"In essence, the thing that limits the smallness of a memory bit for RRAM, MRAM, CBRAM, Memristors, etc, is the select device. A lot of the papers here revolve around different approaches to this problem. Unfortunately, the smallest select devices tend to be the worst behaved. Crossbar says that theirs is better than the rest, and the press release and slides certainly make that case."

When does Handy think RRAM could appear in products?

"I spoke with someone who was in the session [a highly-respected process expert] who lauded Crossbar's promotional efforts but said that the technology is still a long way from production.

"My own position has long been that I see 2023 as the year that this, or some competing technology, will displace flash or DRAM. Entrenched technologies will be with us for some time. Until then, this and all the other technologies vying to replace DRAM and flash will be relegated to niches."

Crossbar RRAM concept

Q and A

We asked Crossbar a set of questions about its technology and this is what Sylvain Dubois, its VP for Marketing & Business Development, said.

El Reg: Your 3D RRAM can scale to a 1TB chip. Current NAND chips are 128Gbits and 3D NAND promises even higher densities. The Crossbar demo chip is 4Mbits. What do you anticipate will be the first commercial Crossbar RRAM chip capacity? If Crossbar's technology has 16x the density of current NAND technology are we looking at 16 x 128Gbits = 2.048GB?

Sylvain Dubois: Our first stand-alone product family will reach 1Tbit per die.

El Reg: Crossbar's RRAM endurance is 10x current NAND. Is that SLC, MLC or TLC NAND, and what is the current NAND endurance value you have in mind?

Sylvain Dubois; MLC NAND is about 10,000 write cycles, TLC NAND is about 1,000 write cycles. Crossbar RRAM is targeting 100,000 write cycles.

El Reg: Is Crossbar's RRAM byte-addressable or or is it addressed in blocks like NAND?

Sylvain Dubois: It is byte addressable for the embedded market (on-chip NVM with processing cores on same silicon die). For storage application, customers prefer small pages, about 1K Bytes pages.

El Reg: How does Crossbar's RRAM technology compare to 3D NAND?

Sylvain Dubois: [Our technology has] CMOS compatible Back-End-Of-Line technology, no specific or expensive manufacturing tools, [and] low manufacturing cost. [It's] scalable to small geometries while NAND flash limit is around 19/16nm.

[We have the] ability to tuck in the peripheral circuitry under the cross point memory array [with] no need for a dedicated "memory fab".

El Reg: How does Crossbar's RRAM technology compare to Phase-Change Memory?

Sylvain Dubois


  • Phase change requires heat to change phase from poly to amorphous and vice-versa. As a result high current is needed to generate this heat. Crossbar RRAM is based on electric field-dependent phenomena and does not involve any phase change of the material.
  • Due to heat PCM is not array scalable as there will be cross-talk between the cells. Due to field-dependency, Crossbar RRAM does not suffer from cross-talk and is highly array scalable.
  • Phase-change is currently using the 1T1R architecture. With the select feature of the Crossbar RRAM, we enable the 1TnR* architecture which gives us the high-density crosspoint arrays.

El Reg: How does Crossbar's ReRAM technology compare to HP's Memristor technology?

Sylvain Dubois


  • HP memristor is based on an oxygen-vacancy phenomena and typically requires noble electrodes like Pt, which are difficult to integrate in the fab. Crossbar RRAM is based on ionic metal motion and does not require noble electrodes to be used. Metal ions are much more reliably controlled than oxygen vacancies.
  • As reported the signal between the ON and the OFF state is low for HP memristor. Crossbar RRAM has a larger ON to OFF signal and it continues to increase as the technology scales to smaller geometries.
  • Memristor technology typically requires a complex non-stoichiometric oxide for oxygen vacancy-based switching and is difficult to replicate. Crossbar RRAM is based on simple amorphous silicon switching layer, does not require tight stoichiometric control and is easy to replicate.

El Reg: You say you are one step closer to commercialization. How many steps are there?

Sylvain Dubois: There are four steps to commercialization. They are basic physics understanding and cell characterization, repeatability proven on small arrays using a prototype, foundry transfer and finally volume manufacturing. We are one last step away.

El Reg: Crossbar has dealt with the sneak path current problem which affects reading of data. Are there problems which affect writing of data?

Sylvain Dubois: The sneak path current problem impacts both reads and writes. What Crossbar is disclosing today solves both reads and writes to high-density crosspoint arrays.

El Reg: What are the read and write 4K IOPS numbers for Crossbar's ReRAM?

Sylvain Dubois: We are not yet announcing product specifications. At the technology level, we demonstrated that we have very low latency random read and small page granularity. We’re currently in discussion with alpha partners to leverage these superior characteristics and performances at the system level.

El Reg: What are the anticipated sequential bandwidth numbers for a Crossbar RRAM SSD?

Sylvain Dubois: We cannot disclose our product specifications at this time.

El Reg: How will Crossbar RRAM be implemented? As an SSD? A PCIe ReRAM card? DIMM modules?

Sylvain Dubois: We will ensure that Crossbar RRAM superior performances will improve the end-user experience by choosing the most suitable bus interface and system form-factor. [The] latest SSDs and DIMM modules seem to match these criteria for our first stand-alone product family.

El Reg says

This is serious technology looking for a semi-conductor foundry partner to commit to manufacture. If Handy is right then we might see niche product emerging in the next 18 - 24 months. It will have to compete with HP's Memristor and Micron's PCM with HGST demoing a PCIe card PCM concept using Micron chips recently. ®

* 1T1R architecture has one Transistor managing one Resistive memory cell. Crossbar says it's 1TnR (1 Transistor driving n Resistive memory cells) selectivity makes it possible for a single transistor to manage a very large number of interconnected memory cells, which enables very high capacity solid-state storage.

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