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Meet AMD's pole-dancing 64-bit ARM chip: Hierofalcon wants to be in a mast near you

Virtual servers, virtual storage, virtual networks ... will it end?

Tangle of cables attached to a telegraph pole

AMD is today pitching its 64-bit ARMv8 system-on-chip codenamed Hierofalcon at software-defined networks in telcos. Essentially, it thinks the processor can do the job of dedicated hardware better, in terms of size and performance per watt.

We're told the processor can have up to eight Cortex-A57 cores, is being sampled by "the usual suspects" in the industry, and will later today, at ARM TechCon in Santa Clara, California, be demonstrated running "Network Functions Virtualization" (NFV). AMD defines NVF as...

the abstraction of numerous network devices such as routers and gateways which enable relocation of network functions from dedicated hardware appliances to generic servers. With NFV, much of the intelligence currently built into proprietary, specialized hardware is accomplished with software running on general purpose hardware.

Imagine, instead of racks of hardware dedicated to various specialist tasks, such as identifying and tracking mobile phone subscribers across cells, you have a box of generic processors that run those functions in software, allowing services to be spun up and spun down on demand, sorta like elastic cloud computing. Some telcos reckon this could be a good way to save power, and AMD wants to be involved.

AMD is busy cooking up 64-bit ARM processors – it just shed more light on its upcoming ARMv8 Seattle chip – but it is best known for its Intel-compatible x86-64 brutes. Why not use beefy x86 to virtualize network functions?

Well, according to Scott Aylor, veep and general manager of the embedded systems division at AMD, ARMv8 was chosen for a few of reasons: one is that ARM cores can be coupled tightly to network interface controllers in silicon to optimize the effort of virtualizing the network functions. These system-on-chips can then be built so that they consume less power than their x86 rivals while allowing enough of them to be packed into small boxes.

That means telco equipment using AMD's ARMv8 silicon can be squeezed into tight gaps, such as on the poles along the streets of Japan's extremely dense metropolises, where space is extremely limited. Here, you can't drop a modest-sized shed of rack-mounted machines and install a tall mast. AMD's 64-bit ARM gear is therefore aimed at places where space and a decent power supply is too great a premium.

"This summer I was in downtown Tokyo. They don't have the luxury of setting down one of these large cabinets; you've got enough space for shoebox-size equipment. Sometimes they have to be fitted to a structure that already exists," Aylor told The Register.

We're also told that developers of virtual networking software – the applications making the decisions – are gradually moving over to, or are now supporting, the ARM architecture. Normally, one would associate the rival MIPS architecture with networking gear processors, but AMD reckons it's betting on the winning horse in that race right now.

"ARM's ecosystem has a lot of momentum, and the power and space efficiencies make it a very good fit," Aylor added.

"NFV is moving very fast, whereas the rest of the industry, the networking industry, takes three to five years to move. Moore's Law went through three generations between [the arrival of] 3G and LTE."

It's possible to accelerate much of the above using FPGAs or ASICs, and install femtocell-like stuff, but AMD insists the ability to reprogram and reconfigure the network structure on the fly is what makes its NVF gear attractive. Aylor admitted that virtualizing right down to layer one in the OSI model is impractical; the latencies would be too great.

Who, why, what, when, how? AMD's diagram accompanying its demo: an ARM system juggling SGW, PGW and MME network traffic

What exactly is being virtualized at this stage? According to those in the know, it's this:

  • S-GW (Serving Gateways): These are used by phone networks to route mobile broadband traffic between cell towers and the wider internet; they can also be used by the feds to intercept packets, and allow telcos to track mobile data use.
  • PDN-GW (Packet Data Network Gateways): This usually sits close to the S-GW, and provides services like IP address allocation, per-user packet filtering and inspection, and produces usage reports for calls, internet access and other things customers can be charged for.
  • MME (Mobile Management Entities): The MME is a vital control system in a mobile phone network; it authenticates and authorizes subscribers, and tracks them across the network.
  • CDN (Content Delivery Networks): Caches that hold popular video files, web pages and other material, and are placed close to the edge of the network so the data can be streamed to users as directly (read: quickly) as possible.
  • DHCP (Dynamic Host Configuration Protocol) servers: The widely used protocol to assign IP, DNS and router addresses to things connecting to a network.

At TechCon this week, AMD plans to demo the system described below: "An embedded Linux-based virtual NFV solution that demonstrates a mobile packet core network running subscriber calls from simulated Evolved Node B (eNodeB) user equipment such as a cell phone or tablet with Serving Gateway (SGW), Packet Data Network Gateway (PGW), and Mobility Management Entity (MME) control and data plane functions hosted on the AMD Hierofalcon platform."

The demo will include live transfer of traffic from an x86 system to the 64-bit ARMv8 chip. Aricent provided the networking software stack, and Mentor Graphics provided the embedded Linux, we're told.

Meanwhile, the Linux Foundation has today announced the founding of the Open Platform for NFV Project (OPNFV), "a carrier-grade, integrated, open source reference platform." ®

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