Samsung: We've slashed programming time with 3-bit vertical NAND
Stack those TLC planar layers high, boys
Korean flash foundry king Samsung has announced the entry of 3-bit (TLC) flash in its V-NAND product line at the Flash Memory Summit.
The product has 32 layers of TLC NAND, TLC being triple-level cell as opposed to the bulk of today’s business NAND products which use MLC or 2-level cell with 2 bits per cell.
TLC NAND is both slower in data access terms and shorter-lived than MLC, with the number of times it can be written counted in hundreds. That means it requires sophisticated controller technology to lengthen its endurance.
The Register was not present at the Samsung presentation but, according to one of several reports, Samsung claimed its TLC V-NAND has a 50 per cent reduction in programming time compared to ordinary planar TLC chips and uses 40 per cent less power as well.
Sammy said a TLC 32-layer V-NAND SSD would arrive soon, and it was breaking through the 10nm process barrier with its tech.We doubt that the V-NAND uses 10nm cell geometry, a 30nm-class being more likely.
It’s speculated that this could be called an 850 EVO and El Reg understands that availability “soon” means before the end of the year and possibly before November. This device could offer capacities of a terabyte or more, 4TB possibly, and be suitable for longer-term storage, unless Samsung has really managed to soup up the endurance in drive writes a day for three or five years terms.
Samsung has also seen lower write latency in its SSDs if accessing hosts co-ordinates with the SSD controller to optimise writes. It says there needs to be a standard interface for this idea to become mainstream. ®