HGST brings PCM to flash show, STUNS world+dog with 3 MILLION IOPS
Wrong tech for Flash Memory Summit - but damn, it's good
In a terrific demo of the wrong technology for the Flash Memory Summit, HGST is showing a PCIe-connected Phase Change Memory device running at three million IOPS with a 1.5 microsecs read latency.
Phase Change Memory (PCM) stores binary digits as differing resistance levels by changing the state, or phase, of the chalcogenide material they are made with from amorphous to crystalline and back again.
PCM devices are said to offer much faster data read speeds than flash and provide a denser memory configuration. But it is an emerging post-NAND technology, with IBM, Micron and others working to develop it – and it's definitely not flash.
Relatively out of the blue, HGST is demonstrating a PCM device built from 45nm 1Gbit PCM dies, supplied by Micron we understand, and using its own controller with a DC Express protocol running across PCIe.
This protocol was discussed at FAST ’14 in February , in a paper entitled “DC Express: Shortest Latency Protocol for Reading Phase Change Memory over PCI Express” and written by Dejan Vučinić, Qingbo Wang, Cyril Guyot, Robert Mateescu, Filip Blagojević, Luiz Franca-Neto, and Damien Le Moal of HGST’s San Jose Research Center; and Trevor Bunker, Jian Xu, and Steven Swanson from the University of California, San Diego; and presented by Zvonimir Bandić, from HGST’s San Jose Research Center. Download the paper here (PDF).
There is a (slow-loading) video of the presentation available by clicking the video image below:
Download video by clicking the image
DC Express very crudely works by getting rid of extraneous PCIe protocol chatter. In the paper the researchers demonstrated 700,000 IOPS from a set of 5 x 1Gbit PCM chips with a queue depth of one. Our understanding is that the three million IOPS comes from moving the queue depth to 4.
Micron PCM chips
The 3 million IOPS was exhibited when randomly reading 512 bytes at a time. The paper says that the PCM device’s write latency is 55 times the read latency, meaning 82.5 microsecs, which is in the MLC NAND write latency area.
There is no information about the capacity of the device. The one discussed in the FAST presentation was 5Gbits. HGST does say that the PCIe card in its demo device is a full-height, full-length, gen 2.0, 4 lane one.
HGST is getting excited about the storage-class memory possibilities with the device – it's being more of a low-cost DRAM replacement than a flash-killer it thinks, but it is non-volatile. The technology prompts the question "Who needs ULLtraDIMMs?" which should exercise the engineers at SanDisk. Perhaps PCM dies could be interfaced to memory DIMMs too?
It is not clear how far away this HGST demo is from a deliverable product, maybe nine - 18 months.
One thought: if it needs a full-height, full-length PCIe card with only 5Gbits of PCM on it then perhaps a lot of work needs doing to shrink the controller logic?
Product-wise are we looking at the development phase start of a FlashMAX IV PCIe PCM card? This'll set the other PCIe flash csrd vendors all a-flutter. If Micron is serious about its PCM technology the it could produce a PCIe flash card too, although it would need its own faster-than-PCIe interface protocol too, to realise the speed potential.
This eye-catching bit of phase change memory kit can be seen at booth 316 at the 2014 Flash Memory Summit, Santa Clara, CA, August 6-7. ®
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