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Cheap, backwards-compatible PCIe 4.0 on track for 2015 2016

16GT/sec interconnect dependent on the kindness of strangers

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PCI-SIG Development of the fourth generation of PCI Express – unsurprisingly dubbed PCIe 4.0 – is moving along nicely, but don't expect the final specification to be completed until at least late 2015 or more likely early-to-mid 2016.

That's the bad news. The good news is that moving up to the new 16 gigatransfers-per-second standard – intended for such data-hungry applications as high-speed Ethernet and InfiniBand, plus HPC and high-end storage – promises to be a smoother transition than was the bump from PCIe 2.0 to PCIe 3.0.

"No funny encoding changes this time around, nothing new – it's basically a straight-up 16-gig," PCI-SIG marketing workgroup chair Ramin Neshati told reporters at his organization's developers conference last week in Santa Clara, California.

"It's mostly a PHY evolutionary play at this point," Neshati said. "Very little in terms of protocol changes, very little in terms of link-level management changes. So, same equalization – well, maybe a bit more robust equalization – but no new back channel and all the various things that happened in PCI Express 3.0."

In keeping with the PCI-SIG's mandate, PCIe 4.0 will be fully backward compatible, both mechanically and electrically, and will require essentially the same amount of power as its predecessor. As the PCI-SIG's president and chairman Al Yanes told us assembled hacks, "compatibility is our bread and butter." You will, for example, be able to plug a PCIe 1.0 device into a PCIe 4.0 connector – and vice versa – and the system will detect and negotiate down to the lowest common denominator.

Details of PCIe 4.0

For data-starved use cases, PCIe 4.0 will be worth the wait – promise (click to enlarge)

Backwards compatibility is an investment-saver, and the PCI-SIG is all about keeping costs down. For example, the doubling of the link bandwidth from PCIe's 8GT/sec won't require any exotic materials, Neshati said. In keeping with the PCI-SIG's commitment to low-cost, high-volume deployments, PCIe 4.0 PHYs will still be fabricated using good ol' FR-4 glass epoxy electrical insulator as their foundation.

It's possible to go faster than 16GT/sec – but not faster while remaining inexpensive, Neshati said. "The technology's out there to go on copper to 32 [gig] with short channels – maybe even higher. We are all about low-cost constrained environments. That's what we are targeting."

Speaking of short channels, PCIe 4.0 will operate over distances around half the length of a traditional server's 20-inch data paths. "The length – the channel run – for PCI Express 4.0 is targeted at 10 to 12 inches," Neshati said, "because at these rates with low-cost FR-4, you cannot drive a signal at 20 inches through two connectors. Ain't gonna happen. Physics will not support it."

Not to worry, though. That 20-inch run can be achieved – you'll just have to add a repeater in the middle of two 10-inch runs. "And guess what?" Neshati said. "We are already defining a retiming device spec – it's called a PCI Express retimer or retiming device – and there is an [engineering change notice (ECN)] that just went out for member review. It came back from member review, and it's looking very healthy, and it should be published very soon."

Separating science from pseudoscience

And that mention of "member review" brings us back to why PCIe 4.0 devices are not likely to appear until 2016.

As of today, the specification is at Rev 0.3, and Neshati told us that "0.3 of the PCIe 4.0, surprisingly, is a lot more detailed than 0.3 of PCI Express 3.0." With that solid foundation, Rev 0.5 is expected in the second half of this year.

Then, however, there will need to be a lot of back-and-forth debate among the PCI-SIG and its member companies: studies have to be done, experiments need to be run, simulations need to be conducted – if you've ever witnessed a standard being developed, you know it's not unlike the proverbial making of sausage.

"One company comes in and says, 'I ran these sims and I saw this'," Neshati gave as an example. "Another company comes in and says, 'I ran the same sims and I saw this other thing.' Then you need to sit down and figure out who did pseudoscience and who did real science. All of that needs to get debated and vetted. It's not easy."

And after the spec gets to Rev 0.7, there's another hurdle to be vaulted: an actual implementation, not just a simulation. "Between 0.7 and 0.9 we typically require some data – some test-chip data," Neshati said. "Some company needs to come in and say, 'You know that 0.7? I actually implemented that and I saw this. And so you know all those parameters that you defined? I'm not seeing the same values here.' So then we have to debate, and discuss, and fine-tune."

But actual physical testing of an actual physical chip before the spec goes final, Neshati said, not only ensures that all will work as promised, it also levels the playing field between those companies with deep pockets – the ones that have the means to make final tweaks on their own – and the rest of the industry.

He also noted that since the PCI-SIG is a voluntary organization, it must rely on one or more of those deep-pocket companies that can afford the highly specialized – read "expensive" – equipment needed to do the final testing and qualification before the spec is released. It can't simply order up a test chip, but must wait for – and possibly cajole? – a member to make the investment.

But when the numerical descriptor of the version under development finally does leap to the left of the decimal point and become 1.0, the entire industry – from rich incumbents to scrappy startups – should benefit.

"I think 'big data' will like this more than others," Neshati said, "but you can go wide and speed for big data, and you can go narrow – like by-one – and speed for other client-like applications. Storage, graphics, whatever, can benefit from Gen 4.

"Graphics can surprisingly go with gen-three for a long time," Neshati said, but added that if you want to narrow the number of lanes on a graphics card – perhaps simply to save money or to cluster a few cards onto the same multi-lane channel for an HPC installation – PCIe 4.0 can help.

You'll just need to wait for that help for a couple of years. But as Neshati assured us, "We not holding things up for no reason. There's actual science going on. There's actual physics going on." ®

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