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Big Blue blasts fibre bottleneck with analog-digital double whammy

New production chip does 128 BEEELLION conversions per second, and new design is EVEN FASTER

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ISSCC Big Blue bade farewell to a bottleneck in data transfer this week with a new analog-to-digital converter capable of up to 180 billion conversions per second, and claimed success in mass producing an earlier design, as well.

This double whammy of news was revealed at the International Solid-State Circuits Conference (ISSCC) in San Francisco on Wednesday, and means Big Blue has successfully turned an analog-to-digital converter it revealed last year into a CMOS-produced chip with partner Semtech, and has made advances on its own design since then.

ADC's are one of the key technologies for transferring data over large distances, and for pulling information off scientific equipment such as radio telescopes. With these new chips, IBM is helping to increase the rate and lower the relative power cost of either pulling information from the physical into the digital world, or transferring it between data centers.

The new mass-produced 8-bit SAR (successive approximation register) ADC chip is capable of 64GS/s (giga-samples per second), and is capable of generating a whopping 128 billion analog-to-digital conversions per second with a total power consumption of 2.1 watts.

The chip was first shown off by IBM at last year's ISSCC, marking an impressively swift transition from the lab into the fab for the young tech.

"Our ADC supports IEEE standards for data communication and brings together speed and energy efficiency at 32 nanometers enabling us to start tackling the largest Big Data applications," beamed Dr Martin Schmatz, a Systems department manager at IBM Research, in a canned quote. "With Semtech as our partner, we are bringing our previous generation of the ADC to market less than 12 months since it was first developed and tested."

Along with the mass production chip, IBM also announced that it had tested a new design that ups the performance even further.

IBM's new lab chip is capable of 90GS/s and is also able to be built in a 32nm CMOS process with an area of 0.45mm square, the company said.

The new chip is capable of a signal-to-noise and distortion (SNDR) ratio of 36.0db at input frequencies of up to 6.1GHz, and 33.0db up to 19.9GHz, all the while sipping a mere 667 milliwatts of power.

In other words, it's smaller, better, and cheaper to run than its predecessor, which was itself considered a major breakthough by the chaps in IBM's lab and the École polytechnique fédérale de Lausanne (EPFL), which helped out in the research as well.

One thing worth noting: the news of this rather exciting chip was almost nullified by some IBM suits who drizzled some marketing syrup over the press release by claiming IBM had "set a new speed record for Big Data" – a rather inelegant way of explaining what a sub-1.0 signal-to-noise ratio input looks like. ®

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