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THIS ONE WEIRD CHIP cuts weight from data centre power bills

Korean boffin designs frugal data clock recovery silicon for 100GBE kit

Next gen security for virtualised datacentres

A Korean scientist whose CV includes 100 Gbps Ethernet for Finisar says he's created an extremely low-power 100 Gbps clock data recovery (CDR) chip to help cut data centre communications power consumption.

As we all know, data centres are power gluttons. Build one as big as the NSA, and keeping it from catching fire is a problem. And alongside all the computers and disks, the other big black hole that electricity gets poured into is the communications infrastructure. CDR is one of those low-level chit-chat things that networking kit needs to do just about constantly, so it's a part of the problem.

That's where professor Hyeon-Min Bae's work at the Korea Advanced Institute of Science and Technology comes in. The Institute, along with spinoff Terasquare, is trumpeting the 100 Gbps Ethernet CDR IC that consumes just 0.75 Watts.

This, they claim, is just one-third the power consumption of current CDRs.

KAIST low power 100 Gbps Ethernet chip

The low-power chip is aimed at the 100 GBE line card market. Terasquare and KAIST claim current line cards use 8W multi-channel transceiver chips that also demand very large real estate (112 cm2). The Korean chip, the company says, can be loaded onto a much smaller 16 cm2 QSPF28 module or 20 cm2 CFP4 module – which also helps pack more interfaces into a smaller space.

Of course, the CDR is only one part of the equation. But since KAIST notes that as long ago as 2006, data centre power consumption worldwide had reached an estimated 60 billion kWh annually, every little bit helps. ®

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