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We can't go on like this for much longer, boffins cry to data centre designers

Whole racks on chips needed or scalability will SLAM into the laws of physics

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The basic equations are easy: as data centres grow they need more computing power, better networking, more electricity and more cooling – a combination which University of California San Diego researchers predict will need whole racks to be shrunk to chip size.

Already, there are outstanding examples of what happens when a data centre starts to challenge its own physical constraints. Witness Facebook's ability to create a micro-climate – complete with rain – inside a data centre, or the way the NSA's mega-data-centre in Utah is suffering from chronic and serious overheating.

Hence, Yeshaiahu Fainman and George Porter have written in Science, the architecture of data centres needs a fundamental re-architecture. Rather than building discrete systems that are then assembled into a data centre, unit-by-unit and rack by rack, they argue that a new generation of systems is needed, designed from the chip up.

Their paper (abstract), Directing Data Centre Traffic, argues that servers and the equivalent of a top-of-rack switch need to be integrated on-chip if future scalability and energy demands are to be met.

To achieve the necessary networking, the boffins argue that on-chip optical networking is a must: “These integrated racks-on-chip will be networked, internally and externally, with both optical circuit switching (to support large flows of data) and electronic packet switching (to support high-priority data flows),” they write.

“Integrating rack-level networking requires more aggressive technology advancements” than are available at the moment, the article states. In particular, Fainman and Porter call for expanded research into nanophotonics to greatly increase the scale of optical comms that can be integrated on-chip.

They also say the optical communications needs to be reconfigurable, in what sounds to The Register a lot like chip-level SDN as it will mean that “by quickly reconfiguring optical paths, changes in traffic workloads can be supported … we need even faster optical reconfiguration and cost-effective integration to support the highly variable traffic flows between individual processors on the chip and among the chips.” ®

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