Extreme ultraviolet litho: Extremely late and can't even save Moore's Law

Why this is none of your DRAM business

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SMC To save Moore's Law, not only will the semiconductor industry need to move to not-yet-ready-for-prime-time extreme ultraviolet lithography (EUV), it will also have to make a costly switch from the current 300mm wafer manufacturing standard to 450mm.

So said Mark Thirsk, managing partner of semiconductor industry consultancy Linx Consulting, speaking at this week's Strategic Material Conference in Santa Clara, California.

"How big are these wafers?" Thirsk asked his keynote audience. "Well, everybody in the US seems to use Rhode Island as measure of area, so a 450mm wafer is 1.99 nano–Rhode Islands. Just so you know."

Although the transition to 450mm wafers is under way, and far less problematic than the bumpy – and still possibly dead-end – road that is EUV, Thirsk said that 450mm won't begin to be used in high volume until 2018.

That's unfortunate, because 450mm's economies of scale – more chips per wafer – are going to be needed to keep Moore's law on track.

Remember, although Moore's Law is popularly referred to as the number of transistors in a given chip area doubling roughly every two years or so, Moore's 1965 paper that inspired VLSI pioneer Carver Mead to coin the phrase "Moore's Law" had a strong cost-per-unit component to it.

Cartoon of man selling 'Handy Home Computers' from Gordon Moore's seminal 1965 paper in Electronics Magazine

Prescient illustration from Moore's 1965 paper, "Cramming More Components onto Integrated Circuits"

Should EUV make it out of the "looks pretty good, but..." stage and onto the fab floor, it'll need to be married with 450mm wafers to get back to Moore's cost-per-bit slope. If EUV fails, the high costs of such optical catch-up tricks as multipatterning and new materials will lower fabs' cost-effectiveness.

"We just cannot stay on the trend we've historically assumed," Thirsk said. Yes, EUV would eliminate the need for costly multipatterning schemes and move fabs closer back to the familiar cost-per-bit improvement slope, "But it doesn't buy us all the way back to the trend."

The future of Moore's Law, as plotted with wafer-size and lithography-type variables

In this DRAM model, today's fabs – the blue dotted line – will increasingly violate Moore's Law

Different types of chips would benefit by different amounts from the advent of EUV – logic chips such as CPUs would benefit greatly, for example, with per-wafer cost improvements closing in on 40 per cent over optical lithography at process nodes of around 19nm.

"But in the DRAM business," Thirsk said, "EUV is not to be laughed at," with cost improvements doubling between 24 nanometers and around 19nm. Although those improvements would only be, say, around 4 per cent at the 19nm node, 4 per cent of the bottom line can be a hefty chunk o' change.

And speaking of such chunks, 450mm wafers – at least when they're first in wide use – will be costly slabs of shiny silicon. The fab folks of the world will need to wait to benefit fully from the cost saving that they'll eventually offer in conjunction with EUV.

That is, if EUV ever appears – there are those who have given up on it already.

From Thirsk's point of view, "EUV is needed. If only we had it – but there are significant challenges there, and probably still a significant chance of failure." ®


In addition to his nano–Rhode Island areal standard, Thirsk also provided a Reg-quality distance metric, referring to 10 nanometers as "one beard-second" – the distance that a beard grows in that period of time. And yes, he's British.

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