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NAND flash chips to beat shrink wrap cash trap with 3D stack

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Stacked 3D NAND chips will make up the majority of the flash chip market by 2017, eclipsing today's dominant chip-shrinking tech as flash makers cram ever-greater capacities into a smaller footprint, according to beancounters IHS.

The tech analysts have produced a chart showing stacked or 3D NAND taking up just over two-thirds of the market by 2017, up from barely one or two per cent of flash chips shipped today.

3D NAND chart

Global Forecast of 3-D NAND's Share of Total NAND Flash Memory Shipments (Percentage of Unit Shipments) Source: IHS Inc Oct 2013.

Why is it happening? Long story short: shrinking NAND flash beyond 19-16nm geometry is proving to be expensive and unreliable as bit values can flip. So, to get more capacity in the same chip footprint, more layers of flash cells are added to the chips.

Samsung is doing this with its V-NAND technology, announced in August.

Dee Robinson, IHS's senior analyst for memory and storage, provided the canned backing quote for the chart: "There’s widespread agreement that just one or two generations may be left before NAND flash made using conventional planar semiconductor technology reaches its theoretical limit. As lithographies shrink further, performance and reliability may become too degraded for NAND to be used in anything but the very lowest-cost consumer products."

Stacking layers on the chips enables capacity increases to keep on coming as well as, hopefully, lowering the cost/bit.

The IHS bods also say: "This will be the most cost-effective way of pushing NAND to the next level because most of the existing manufacturing equipment can continue to be used, minimising expenses while maximising return on investment," although "failure analysis will be difficult because of the multi-level structure of the device." ®

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