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It is not just about the core

The "uncore" portions of the new Xeon E5 chip has an improved snoop directory, which moves from one-bit to two-bit (but don’t call it a two-bit snoop directory, mind you) that is enabled in all variants of the Ivy Bridge-EP. This prior snoop directory was only available on the four-socket variants of the Sandy-Bridge-EP chips and was disabled in the two-socket variants.

Now it is enabled on the two-socket Xeon E5-2600 v2 and will presumably be available on the Xeon E5-4600 v2 when Intel gets around to launching them for four-socket machines. (No word on that from Chipzilla at this point).

The L3 cache controller has had the bits doubled up to two as well in its least recently used (LRU) unit, which Steiner says improves cache hit rates. The twelve-core variant has three rings and two memory controllers instead of two rings and one memory controller, which allows for the cache bandwidth to scale linearly with the core counts.

The PCI-Express 3.0 controller on the die supports x16 non-transparent bridge (NTB), up from x8 on the Sandy Bridge-EP chips, and this is a feature that is largely targeted to the high-end of the storage market, according to Steiner.

This allows CPU-to-CPU linking across server nodes over the PCI-Express bus, and is used to run RAID 5 and 6 data protection code over multiple processors embedded in mult-node disk controllers. The PCI-Express controller also has deeper queues and improved arbitration to boost bandwidth as well as some latency reductions that will be handy for HPC customers.

There are eighteen members of the E5-2600 v2 family, and here they are without further ado:

The new Xeon E5 v2 processors

Intel is grouping the chips based on their capabilities, and just to be confusing, these groupings have nothing to do with the three different variants of the Ivy Bridge dies with six, ten, or twelve cores on the chip.

The Advanced chips have DDR3 memory running at 1.87GHz and their QPI links run at 8GT/sec, with the exception of the E5-2650L v2, which has memory running at only 1.6GHz. The four Standard variants of the Ivy Bridge-EP chips have memory running at 1.6GHz and QPI links that run at 7.2GT/sec, while the two Basic variants step down the memory to 1.33GHz and the QPI links to 6.4GT/sec.

There is a Xeon E5-2687W targeted solely at two-socket workstations, which has eight cores and which runs at 3.4GHz. It burns at 150 watts and has memory and QPI links cranked up to their full speeds.

If you want to make comparisons, which El Reg loves to do, here are the feeds and speeds of the prior Sandy Bridge-EP chips:

The Sandy Bridge-EP Xeon E5 v1 processors

On a very rough basis, the price/performance of the two Xeon E5-2600 families is the same, as you can see from the Cost Per Ooomph stats in the two tables above. Oomph is the number of cores times the clock speed, which is a very rough indicator of raw performance within a processor architecture. Yes it is imperfect.

Pricing is the traditional per-unit cost of the chips when bought in 1,000-unit trays from Chipzilla. But there are some interesting comparisons to make that show you can get either more bang for about the same buck or the same bang for a bit less buck.

First, look at the eight-core E5-2667 v2 running at 3.3GHz and sporting a 25MB L3 cache; this chip costs $2,057. The most similar E5-2600 v1 part is the top-bin E5-2690, which was the top-bin part and which cost the same $2,057, but the Ivy Bridge variant delivers about 14 percent more performance and 5MB more of L3 cache to boot.

The ten-core chips run at slower clock speeds, and offer better bang for the buck using the raw Oomphs. But some apps won't scale across 20 cores and 40 threads, so this extra computing capacity might be lost on them.

As you might expect, the two top-bin twelve-core Ivy Bridge chips in the lineup are the most expensive ones in the line and also have the worst bang for the buck, yielding profits for Intel from those customers who need more cores. It will be interesting to see if server makers try to charge a premium for the other Ivy Bridge-EP chips and therefore boost their own profits or just slide them into their existing machines at roughly the same prices.

The temptation is no doubt there to try to get some profits on the front-end of the Ivy Bridge wave among server makers, but with the cut-throat pricing in the server market these days, that probably won't happen and Intel will be the one getting whatever profits there are from the new CPUs. ®

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