Top chip baker: Rough times, high costs, tech hurdles ahead
GlobalFoundries CEO laments EUV tardiness, promises rolled-up sleeves
SEMICON 2013 Ajit Manocha, the CEO of wafer-baker GlobalFoundries, sees plenty of choppy waters ahead for the good ship Moore's Law – and warns that navigating them will be increasingly expensive.
As chip-baking processes shrink, it's getting more difficult to develop manufacturing techniques at a reasonable cost. Breakthroughs are needed even at the upcoming 14-nanometer process node, Manocha told his keynote audience at SEMICON West 2013 on Tuesday in San Francisco.
Unfortunately, the breakthrough that chip-manufacturing foundries – or "fabs" in the vernacular – have been most hoping would come to the rescue isn't yet ready for prime time.
That would be extreme ultraviolet lithography – EUV – which would radically reduce the wavelength of the electromagnetic spectrum used in chip-baking lithography, thus making it easier to reduce feature sizes on chips.
"EUV," Manocha almost sighed when addressing the subject in his keynote. "This is a highly debated topic. We talk about this all the time," he said. "We all know that EUV is late."
EUV is not only important because of its benefits in terms of smaller feature sizes, it's also about cost. Using current technology to craft lower and lower process sizes drives up the lithography costs drastically as a percentage of the total cost of producing chips. At the 14nm level, for example, current lithography technology creates design and operation costs significantly higher than EUV would, according to Manocha.
"We desperately need EUV," he said, "and EUV is still not ready."
As the current lithography technology is pressed to create smaller process sizes, vexing problems arise in areas such as mask defects, resist types, and the like – problems that could be more easily solved with the much shorter wavelength of EUV. "All these issues are being addressed by many, many people in this industry – but we are not ready with EUV. Nobody is ready with EUV."
Lithography is not the only challenge that Manocha sees facing the effort to shrink process technology down through the next few nodes – from 20nm to 14nm to 10nm to 7nm and beyond. "The next one is packaging," he said, citing such needs as improved processes to stack layers of dies – CPU, GPU, memory, specialized accelerators, and the like – one on top of another to reduce chip footprints in mobile devices and enhance communication speeds among chip functions.
Manocha didn't mention one other problem with die-stacked packaging that has also been discussed in the industry: the fact that die testing has to be improved and made more logic cell–specific – perhaps even transistor-specific – so that if you can find a hidden defect in a logic cell in one die before its packaged you won't waste the other perfectly good dies that you would have already stacked with it.
Costs are also a concern due to the number of masks needed in chip manufacturing. Back in the far-distant days of 180nm process, Manocha said, 15 to 20 masks were needed in the photolithographic process of chip manufacture. At 14nm, that number has grown to 60, "plus or minus," he said. The more masks, the more complexity; the more complexity, the higher the cost.
"Something goes wrong, you have to start all over again; 60 mask layers, typically 1.5 days per mask layer, 90 days gone," he said. "Product life-cycle, very short." EUV would help. A lot.
In addition, although GlobalFoundries is moving right along on its 14nm FinFET transistor technology development, Manocha said, it's not putting all of its eggs in that "3D" vertical-gate basket. (Intel calls it's version of FinFET "Tri-Gate"). "We're also working very closely with FD-SOI," he said, referring to the fully depleted silicon-on-insulator planar transistor technology that leverages a lot of the existing investment and design in non-3D transistors.
GlobalFoundries, Manocha said, is also looking at more-esoteric technologies such as carbon nanowires and a variety of "III-V"* semiconductor materials – so named because they are compounds of group III elements such as aluminum, gallium, and indium with group V elements such as nitrogen, phosphorus, arsenic, and antimony, with one promising combo being gallium arsenide, or GaAs.
Technology challenges, design challenges, lithography challenges, materials challenges – it all adds up to cost challenges. "A fab used to be a couple of billion dollars during the time of 130 nanometer technology," Manocha said. "Today? Seven billion dollars." ®
Group III elements are also known – almost exclusively, these days – as group 13 elements, and group V as group 15. If you know why the semiconductor materials are still called III-V (pronounced "three-five") and not 13-15 – other than tradition and marketing, that is – please let your puzzled Reg reporter know in Comments. Thanks.
Sponsored: DevOps and continuous delivery