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Big Blue etches silicon nanophotonics with regular chip tech

Exterminate! Copper wires, Exterminate!

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The path to exascale supercomputing computing is going to require the development of a number of technologies, and one of them is the shift from copper to optical signaling between chips in a complex of computing and memory. And IBM thinks it is going to have an edge in this effort now that it has cooked up photonics components that can be etched with normal CMOS processes and meshed with other electronic components on a silicon wafer.

In a somewhat comical flashback, in its announcement of the silicon nanophotonics breakthrough, Big Blue referred to the waveguides that bring the data-encoded photons into the chips as "information super highways." How's that for a flashback to the mid-1990s?

The research that IBM is unveiling this week at the IEEE's International Electron Devices Meeting (IEDM) in San Francisco builds on work done by Solomon Assefa at IBM Research.

Big Blue made a lot of noise about its silicon photonics research two years ago when it demonstrated that after more than a decade of experiments that it could use standard CMOS processes to make photonics components. Back then, IBM was showing off project Sniper, short for silicon nanoscale integrated photonic and electronic transceiver. (Yes, the changed the T to an R to make it sound cooler.)

The Sniper chip, which included a ring oscillator, a receiver amplifier, a transmitter modulator driver, waveguides, an edge fiber coupler, a wavelength division multiplexer (WDM), a germanium detector, modulators, and switches was implemented in a mix of 130 nanometer and 65 nanometer processes.

The big breakthrough that IBM is talking about today at IEDM is that it has been able to squeeze the photonics features down to 90 nanometers and at the same time integrate them on a regular chip using optical waveguides.

Optical waveguides, in blue of course, on IBM's silicon nanophotonics chip

Optical waveguides, in blue of course, on IBM's silicon nanophotonics chip

IBM's presentation abstract says that the 90 nanometer CMOS process it is using is "optimized for analog functionality to yield power efficient single-die multichannel wavelength-mulitplexed 25Gb/sec transceivers."

The company says that with a few tweaks to the CMOS processes, it can add all kinds of silicon nanophotonics components, such as wavelength division multiplexers, modulators, and detectors, to chips and integrate them side-by-side with other electrical circuitry.

By using a standard CMOS process, these components can be added at less cost – how much less, IBM has not said – and therefore could start being integrated into chips and allowing for the transmission of terabits of data between chips without the use of wires.

Stacking up chips to make tiny Daleks for the data center

Stacking up chips to make tiny Daleks for the data center

As we all know, because fiber optic cable has replaced a lot of coax and twisted pair cable in the world, a laser using photons can transmit signals between chips at higher bandwidths and with lower energy than an equivalent metal wire relying on electrons for signaling.

Photons inside of fiber optics or other wave guides generally move faster than electrons in a wire, too, which means you can possibly get lower latencies by switching from electronics to photonics for signaling.

The problem is that integrating tiny lasers with chip components has been costly. If IBM can do it with 90 nanometer processes today, that probably means it can figure out how to do it with current 32 nanometer processes before too long, and therefore IBM will be able to create cross-chip switching systems based on photonics to transmit terabits per second of data between distinct elements of the system.

The transceiver that IBM is showing off today at IEDM can pump 25Gb/sec per channel. The 3D chip stack down above is just a conceptual block that might be the foundation of future exascale-class systems, integrating processing, coprocessing, memory, and switching all into multichip, stacked modules, linked by lasers. You would gang up lots of the waveguides together to link elements of chips to each other inside of the multichip modules, and then use presumably beefier silicon lasers.

Two years ago, IBM said it would take 100 million optical channels to reach an exascale performance level in a single system, and by the way, that was more optical channels than existed in all of the networks of the world then.

With the CMOS integration and shrinkage that IBM is working on, it may be able to get the photonics issue solved and then move onto getting faster and lower-power memory to slide into the 3D stack. This is where the real bottleneck – and heat production – in such systems is going to be. ®

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