China to strut eight-core Godson-3B MIPS chip in early 2013

Server chip makers take Moore's Law breather – at their peril

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People talk about Moore's Law as if server chip manufacturers had to obey it like some kind of cosmic speed limit. In reality, Moore's Law is an idealized goal, and one that is increasingly difficult to attain year after year for server microprocessors.

This is made clear in the just-released schedule for next year's first big chipmakers confab.

There has been more waning than waxing in the pace of innovation for server chips in recent years, and it looks like server chip makers will be resting on their laurels a little bit as 2013 gets going. That will no doubt make the Chinese Academy of Sciences happy as it discusses a new MIPS-derived Godson-3 processor that packs a big punch in a small wattage.

On processor day when the IEEE's International Solid-State Circuits Conference (ISSCC) opens next February, the chipheads that attended the Hot Chips 23 conference back in August will probably think they're having flashbacks. Just take a peek inside the advanced program for the conference, which is being hosted in late February in San Francisco.

IBM will dust off the presentation for its four-core System z12 mainframe engines, which were detailed back at the Hot Chips 24 conference in August and which are used in the System zEnterprise EC12 machines. These processors spin at 5.5GHz and will very likely be geared down to run in midrange mainframes sometime early next year.

It also looks like Oracle will recycle the presentation for its sixteen-core Sparc T5 processor, which was also discussed in detail at Hot Chips this past summer, as well as give an entirely separate presentation on the glueless interconnect and power management of the Sparc T5 systems.

The Sparc T5 systems are expected to ship in early 2013, and the wonder is that given all that Oracle has already said about the Sparc T5 chips, the company did not decide to talk about its own Sparc M4 chips, which are to be used in higher-end systems spanning up to 32 sockets and which are due next year as well. Oracle has said very little publicly about the Sparc M4 chips,

At ISSCC, Fujitsu will show off its forthcoming "Athena" Sparc64-X processor, which sports sixteen cores as well, but which is intended for beefier shared-memory systems. Fujitsu discussed the Sparc64-X chips at Hot Chips and then talked about the Athena systems that use these processors at OpenWorld in October.

Oracle has been rebadging Fujitsu systems using Sparc64-VI and Sparc-64-VII processors for the past six years (well, Sun Microsystems started it when its own "Millennium" UltraSparc-V chip project failed). Oracle and Fujitsu are going their separate ways in 2013, creating distinct Sparc processors and servers running the Solaris variant of Unix.

IBM talked about the Power7+ processors back at Hot Chips, but is not bothering to repeat it at ISSCC in February. Intel does not have a server processor that it will show off, either, although there are certainly "Ivy Bridge" Xeon E5 and E7 chips in the works for delivery next year.

And while AMD will talk about its "Jaguar" processors for PCs (and maybe low-powered servers) during next year's ISSCC, as it did last summer at Hot Chips, oddly enough the company is not scheduled to talk about the future "Steamroller" Opterons that CTO Mark Papermaster hinted at during Hot Chips.

So what is interesting at ISSCC next year? The eight-core Godson-3B1500 MIPS chip, for one thing.

Weiwu Hu, chief architect of the Godson processors developed by the Institute of Computing Technology (ICT) at the Chinese Academy of Sciences, is coming back to ISSCC to talk about the line of MIPS chips that the Chinese government is funding for handhelds, PCs, servers, and supercomputers. Hu gave a presentation about the Godson lineupat the ISSCC 2010 conference.

This time around, ICT will show off a 32-nanometer shrink of the Godson-3B line, this one called the 1500. The Godson-3B chip debuted back in 2010 in a 65nm process with 685 million transistors across eight cores running at 1GHz and delivering 128 gigaflops of double-precision floating point math performance.

With the shrink to 32nm, ICT will be able to crank the Godson-3B1500 to 1.35GHz and deliver 172.8 gigaflops in a 40-watt power envelope. That's 4,320 megaflops per watt – a pretty impressive number for a CPU, and one that even rivals some accelerators.

By comparison, an Intel Xeon E5-2660, which has eight cores running at 2.2GHz, comes in at 282 peak theoretical gigaflops, but in a 95-watt thermal envelope. That works out to 2,964 megaflops per watt. If you go down to fastest 80-watt Xeon E5 part – the E5-2609 – with four cores running at 2.4GHz, you only get 1,920 megaflops per watt. The high-end 135-watt Xeon E5-2690 gives you only 2,750 megaflops per watt, and the 115 watt Xeon E5-2670, 2,893 megaflops per watt. (Those are all theoretical numbers comparing peak floating point throughput to the peak thermal design point.) The Godson chip is doing better on the basis of thermal efficiency.

Until you bring out the GPU and x86 coprocessors, that is. Provided your code can run on these accelerators, it's tough to beat them in terms of flops per watt. (A lot of code has not been ported to accelerators, and some will be very tough indeed to port over.)

A Xeon Phi 5110P coprocessor from Intel with 60 Pentium cores running at 1.05GHz can deliver 1.01 teraflops peak in a 225-watt thermal envelope, which works out to 4,493 megaflops per watt. An Nvidia Tesla K20X GPU coprocessor delivers 1.31 teraflops peak in the same 225-watt power budget, or 5,822 megaflops per watt.

The Godson-3B1500 has 1.14 billion transistors, with a lot of the extra ones coming from the doubling-up of the L3 cache memory to 8MB, shared across those eight cores. The Chinese chip runs the MIPS64 instruction set and is absolutely compatible with Linux. Windows is unlikely to run native, but the Godson-3 family of chips do have an extra 200 instructions added to the MIPS architecture that allow it to run the QEMU emulator close to the iron and therefore emulate x86 code on top of MIPS.

So, in theory, yes, it can play Crysis.

The ICT roadmap from back in 2011 showed a sixteen-core Godson-3C processor peaking at 2GHz and delivering 512 gigaflops at double precision. This chip was to be implemented in a 28nm process and was originally slated to ship in early 2012 or so. Thus far, ICT has not said much about this Godson-3C, but that would also be interesting to look at.

Another interesting chip that will probably be previewed at ISSCC is an eight-core ARM-based system-on-chip from Samsung Electronics. As El Reg previously reported, this octo-core design will have four little Cortex-A9 cores running at 1.2GHz and four big Cortex-A15 cores running at 1.8GHz with 2MB of L2 cache across the cores. Depending on the job, the little or big core blocks are activated to run apps.

This chip could be the 28nm quad-core Samsung chip referred to in the ISSCC advanced program on page 23 (it is a bit vague), and it might find uses outside of mobile devices. For some server applications, such as media streaming, 32-bit processing works fine and a big.Littledesign , as AM calls it, might offer some advantages. Perhaps Samsung will talk about the possibilities. ®

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