The new Integrity BL860c, BL870c, and BL890c i4 machines have the same BladeLink technology for creating SMP configurations out of two-socket Itanium blade servers as the Integrity i2 generation machines launched two and a half years ago.
But the new blades have a new memory subsystem that supports 1.35 volt DDR3 memory. The blades also sport the same FlexFabric network interface cards that snap into the ProLiant BL series of Xeon E5 blade servers.
The c7000 chassis stuffed with four BL870c i4 servers
The base blade in the new Integrity server lineup is the BL860c i4, which is a full-height blade and plugs into the BladeSystem c7000 chassis that came out six years ago. The c7000 has room for eight full-height blades; the BL860c i4 blade can also be plugged into the "Shorty" c3000 deskside (sorta) chassis, which has room for four full-height blades.
Two silly questions: what happened to the i3 generation of machines – or does Intel own that trademark – and why isn't the base blade called the BL820c, meaning two base sockets scalable to eight sockets, with BL840c and BL880c being the names of the fatter configurations? It's not important, but informative names can actually mean something and actually help you understand the product.
You can use any of the four Itanium 9500 processors that Intel announced on Thursday, ranging from the low-end Itanium 9320 with four cores running at 1.73GHz with 20MB of L3 cache, all the way up to an eight-socket Itanium 9560 running at 2.53GHz with 32MB of L3 cache.
The BL860c has three PCI-Express 2.0 x8 peripheral slots and four FlexFabric ports for linking out to LANs and SANs that run at 10 Gigabit Ethernet speeds. The blade has two hot-plug SAS drives in a 2.5-inch form factor for local operating system storage, and HP offers 146GB, 300GB, 450GB, 600GB, and 900GB disk drives as well as 200GB and 400GB flash SSDs as storage options.
Now, say you need more capacity to run your HP-UX workload. Buy another BL860c i4 blade, slide it into the chassis, snap on the BladeLink across the front and – Bam! – now you have a four-socket server that is bridging across the QuickPath Interconnect (QPI) links on the Poulson chips and the "Boxboro" 7500 series chipset.
This four-socket blade is called the BL870c i4, but it is really just two BL860c i4 machines with a BladeLink. If you need more oomph than that, you can put in two more two-socket blades and two more BladeLinks and – Bam! Bam! – you now have an eight-socket SMP box. There's enough room in the c3000 for one eight-socket machine, and the c7000 has enough room for two. If you want a six-way SMP box, you can build an eight-socket machine and half-populate two of the blades; you can't snap three of the blades together because of the way the chipset and QPI links work.
The initial Integrity i2 blades only supported 4GB memory sticks at 1.5 volts, with 8GB sticks offered later. With 24 memory slots per blade, this limited main memory to a maximum of 96GB. With the i4 machines, HP is shifting to 1.3 volt memory and is supporting 4GB, 8GB, or 16GB sticks. Presumably 32GB sticks will come out shortly, thus boosting capacity to 768GB per blade.
Kirk Bresniker, an HP Fellow and chief technologist for the BCS division, did not divulge when fatter memory would be available, but El Reg would bet it can be special-ordered if you really need fatter memory. In the meantime, you'll have to buy more blades. With all four blades lashed together, you can bring 1.5TB to bear on a single system image, which is in the same ballpark as the latest Xeon and Opteron servers.
By the way, you can mix and match Tukwila and Poulson processors within a single c3000 or c7000 enclosure, but you can't mix and match them within a virtual or hard partition. – all of the processors have to be the same inside a partition.
One more thing: The nPar electrically isolated hard partitions of the Superdome 2 machines have been migrated down to the i4 blades. You need at least four sockets (and hence two blades) to make an nPar.
Next page: Scaling the Superdome 2
You've gotta be kidding Matt.
Yes, I've also seen the HP sales manual for how to sell against POWER, that what you get from partnering with everyone. That doesn't mean that it's right.
Do you seriously think that a 8 socket Poulson Blade with limited IO, limited Memory, can compete against a POWER7+ based POWER 770/780 with 16 sockets, fullblown IO and Memory ? And hotswap of everything ?
That is in Kebabbert territory of fanboiship. You should know better.
I think the HP Poulson blades looks like a solid product, but it's not remotely in a position to compete against POWER 770 or 780's.
Now I have no doubt that the bl890 i4 will be able to beat the PS704 blade, but again that is a 2.4GHz POWER7 system, in a form factor that I would never use for enterprise computing.
And you say it yourself.. partitioning... POWER stopped doing partitioning back in 2005. You know ... it's kind of a bugger to claim that you have the best moped, when trying to win a race against someone in race car. Nobody ... except SUN and HP talk about partitioning anymore... and HP does actually have a decent virtualization option.
You do understand why the Itanium implementation of an EPIC architecture needs large caches to generally perform well right ? And caches that are much larger than for example x86 and RISC's.
You do understand that the fact that you try to claim hilarious things like "And IBM does not have good cache hit ratios as Intel so the faster SRAM is even better in practice.", (in the context of Itanium) shows that you don't really understand the whole idea behind Itanium ?
RTFM Matt, my first compile and testing of Itanium was in January 2001, on an Intel 'whitebox'. And I've been using the architecture on and off since then.
Merced 1 core 800 Mhz 0MB L3 cache 0 MB L3 cache per core
McKinley 1 core 900 MHz 1.5MB cache 1.5MB L3 cache per core
McKinley 1 core 1 GHz, 3MB cache 3 MB L3 cache per core
Madison 1 core 1.5 GHz, 6MB cache 6 MB L3 cache per core
Madison 1 core 1.67 GHz, 9MB cache 9 MB L3 cache per core
Montecito/Montvale 2 cores 1.66 GHz, 24 MB L3 cache 12 MB L3 cache per core
Tukwila 4 cores 1.73 GHz 24 MB L3 cache 6 MB L3 cache per core
Poulson 8 cores 2.53 GHz 32 MB L3 cache 4 MB L3 cache per core.
So basically the amount of L3 cache that is in Poulson brings us back to the day of McKinley, in the L3 per core ratio. And furthermore Poulson uses HW multithreads, which makes it even worse, in comparison to for example Madison.
For comparision POWER7+ has 80MB L3 cache, which is actually very clevery divided into two parts a local and a 'not so local', which speeds up access of 10MB of the L3 cache per core.
And last rumours has it that haswell will using eDRAM,
"No, all frequencies quoted for IBM CPUs are from IBM brochures."
Nice attempt at ducking.
"Well, using the phrase "up to 4.1GHz" doesn't sound very guaranteed!"
You are simply not making sense. You are mixing thing up, purposely misinterpreting numbers and drawing conclusion that have nothing to do with reality.
It's very simple. A 8 core 4.1GHz POWER7+ processor will run flat out at 4.1GHz on all cores if you provide provide load for all cores, and provide the cooling and airflow specified in the manuals.
If you specify in the energy policy for the system that the system should optimize energy usage over performance the system will do so. Including the cores, hence it will put cores and processors for that matter into states that uses less energy if there isn't load enough to provide work for these cores processors, IO slots whatever.
If you specify in the energy policy for the system that it should prioritize performance over energy usage it will try to boost the frequency of the cores when it's needed.
If you are using a POWER7 system booted up in TurboCore, mode, the cores that are activated will run at a boosted frequency rather than the normal frequency all the time, there will be no aditional frequency boost available, according to the manual.
Actually it's much like what Intel is doing with it's Xeon processors. It's actually pretty simple.. or at least for everyone else than you.
"It's still not "3-4x" as claimed by the other IBM troll, though"
Power 7+ has 80 MB across 8 cores. Poulson will have 20-33 MB across 8 cores... or 25% to 41% that of Power 7+. I suppose it is technically 2.42-4x the amount of L3 cache, but, point being, a ton more than Poulson.
"So IBM gurantee you will have all eight cores spining at 4.1GHz?"
The IBM data sheet has four procs in the 770 CECs at 4.42 GHz. Again though, we are talking miles apart. Call it 4.4, 4.1, 3.8.... much faster than anything Poulson can provide is the point. You are splitting hairs to determine if P7+ is much faster or much, much faster than Poulson. If you determine it is much faster, is that some sort of victory for Poulson? The highest clock speed even *claimed* by HP is 2.53 Ghz... probably subject to the same thermal caveats you claim to be true for Power. Power 7+ fully clocked down will still be considerably faster than Poulson top bin.