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ARM busts out server-to-superphone superchips

Low-power juggernaut takes two more steps towards world domination

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ARM TechCon ARM has rolled out a new series of processors – the Cortex-A50 Series – that it says will find their way into everything from smartphones to mega-data centers.

The beefier member of the two-chip series has already found at least one data-center home in future ARM-based Opteron server chips, as announced this Monday by AMD.

The processor design that AMD chose, the high-performance Cortex-A57 (formerly code named "Atlas"), was unveiled along with its low-power sibling, the Cortex-A53 (née "Apollo"), by ARM processor honcho Simon Segars during his keynote on Tuesday at the ARM TechCon 2012 conference in Santa Clara, California.

Describing the A57 as "the highest-performance processor from ARM," Segars said that it would provide "PC-class performance in a superphone power envelope." (An ARM spokesman told us that by "superphone", ARM means devices such as the Samsung Galaxy S III and the iPhone 5.)

The Cortex-A53, on the other hand, was described by Segars as "the most energy-efficient processor that we have built," providing superphone-level performance at not only low power levels, but at low cost as well.

Simon Segars, EVP and general manager of ARM's Processor and Physical IP Divisions, at ARM TechCon 2012

Both the A57 and A53 employ the 64-bit extensions to the ARMv7 architecture that were announced when the 64-bit ARMv8 architecture was unveiled last October at that year's ARM TechCon. They're not limited to 64-bit code however; they'll also run existing 32-bit code without a hitch, thus easing the transition to the inevitable all-64-bit, all-the-time future.

In case it is not too obvious, we'll point out that to run both 32-bit and 64-bit code, the operating system being run on the A53 and A57 will have to be 64-bit. But you knew that.

ARM Cortex-A57 description

ARM forsees Cortex-A57–based platforms containing 16 cores or more

The A57 is essentially a Cortex-A15 with the addition of the ability to handle 64-bit processing, along with other performance and architectural tweaks such as improved floating point and added crypto capabilities.

Like the A57, the A53 has a progenitor: the Cortex-A7. Despite that somewhat lowly background, AMD claims that the A53's performance will equal that of the beefier A9, the core found in many of the world's current smartphones superphones.

One other interesting detail about the A53 versus the A9 is that ARM claims that even when baked using the same 32-nanometer process as is used for the A9, the A53 will take up only 60 per cent of the same die area, despite the fact that it will offer 64-bit goodness compared with the A9's 32-bit operation.

ARM Cortex-A53 description

ARM's smaller, lower-power Cortex-A53 can stand alone or live on the same die as a Cortex-A57

And when you shink the process used to bake the A53 down to 20 nanometers – which is what ARM projects its customers will use when their chips start appearing in 2014 – and the A53 will require only about 25 per cent of the real estate of the suddenly obese A9.

Importantly, the A53 and the A57 are not only designed to be used alone in appropriate systems, but also together on the same die in implementations that ARM has unfortunately dubbed "big.LITTLE", also announced last October.

The idea behind big.LITTLE is simple: mix hefty cores and wimpy cores on the same chip, and when the chip needs to perform something that requires high performance, kick in the out-of-order, muscular A57. When the device is just loping along, say, opening an email, shut down the A57 and have the low-power in-order A53 do the work.

As a result, the user of the device percives high-powered performance when the A57 is needed, and battery savings when compute needs are easily handled by the much more power-miserly A53. And since both types of cores are running code based on the same instruction set, the system can handle the traffic management transparently to the user – and AMD says that the A53 will be the one taking care of business the majority of the time.

ARM 'big.LITTLE' performance chart

Use the "big" core only when needed, with simpler stuff on your "LITTLE" core, and the performance/power relationship improves

The A53 and A57 won't be the first ARM cores to be coupled in a big.LITTLE scheme. The company now has A7 and A15 cores so married, and claims that performance gains and power savings are impressive. Expect A7/A15 mashups using big.LITTLE to appear in products next year, they say.

ARM expects to have A53 and A57 silicon in its labs for extensive testing by mid-to-late 2013, although it would not be at all surprised if some of the partners with whom it is working – AMD, Samsung, Calexda, Hisilicon, Broadcom, and STMicroelectronics – to beat it to the punch.

Products based on the AMD Cortex-A50 Series should begin to appear in 2014 – which, not coincidentally, is when AMD says to expect its first 64-bit, ARM-based Opteron server chips. ®

Bootnote

During Segars' keynote, he hosted a wide-ranging discussion with reps from AMD Cortex-A50 Series partners, discussing among other things how the data center is evolving and specializing as the range of workloads being run proliferates. When he asked them to speculate what the data center might look like in five years, SeaMicro co-founder and now AMD data center guru Andrew Feldman had an interesting take.

"In five years we will look back at how we deliver compute today," he said, "and scratch our heads in the same way that we look back at the 1960s spy shows like The Saint, and say, 'Oh, that's quaint, and what a cute car, and that's a trendy suit he's wearing.' We say these things that are laughable about the shows from that era, and as we think about the size of the facilities that we will build, how we organize compute in those, which instruction sets are used in that compute ... these facilities will be profoundly different."

If the ARM-based data center takes off big-time, will we someday think of Intel CEO Paul Otellini as being as "quaint" as Simon Templar?

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