IDF 2012 The low-voltage performance of Intel's 22-nanometer chip-baking process turned out better that the company had predicted, and the development of next year's 14-nanometer process technology is proceeding swimmingly, thankyouverymuch.

So said Chipzilla's head of process technology, Mark Bohr, speaking at a tech session during the company's Intel Developer Forum in San Francisco on Wednesday.

And he should know. Bohr is a senior fellow in Intel's Technology and Manufacturing Group, and the director of the company's process architecture and integration efforts. In simple terms, he creates the stuff that chips are made of.

He was also the unfortunate star of Mark Bohr Gets Small, an Intel-created video that attempts to explain the tri-gate transistor technology that debuted in Intel's 22nm "Sandy Bridge" chips. That technology, Bohr told his IDF audience, "looks like it's going to be extendable to a couple more generations, as well."

It also turned out better than expected. Armed with an array of charts and graphs, Bohr explained how the tri-gate transistors' current leakage and sub-threshold slope – essentially the voltage rise before a transistor turns on – were more efficient than Intel had predicted they would be.

"What we're running in production is better than what we announced in May of last year," he said. That's A Good Thing™ — both contribute to a processor's low-voltage performance by allowing transistors (all else being equal) to perform better and use less power.

Bohr also discussed the progress of Intel's next process shrink. "The 14-nanometer technology is in its full development phase," he said, "and it's on track for production readiness around the end of next year."

Not that the shrink is going to be an easy one. The transistor pitch – essentially the distance between two transistors – in the 22nm tri-gate technology is 80nm, which is the smallest pitch that can be produced using single-pattern lithography, Bohr says.

"The next generation, 14," he said, "we're going to have to convert to double patterning to get tighter pitches." Double patterning – as might be obvious – requires an extra step in the lithography process. An extra step – equally obvious – adds extra cost.

'I have seen the future, and it's ... well ... not terribly clear yet' (click to enlarge)

But that won't make 14nm chips more expensive, Bohr assures us. "Although wafer cost is going up, it's still being offset by the improved density," he said. "At least for Intel, our cost per transistor continues to go down with each generation on a very steady trend, from 32 nanometers to 22 nanometers to 14 nanometers."

Cost is not the only challenge in moving down to 14nm, Bohr said. For one thing, there's the problem of creating the interconnects in a chip so dense with transistors. "Well, you've got skinnier wires," he said, "and can you get copper stuffed into that shallow trench with good reliability, good performance? We have that challenge."

But the interconnect challenge is still on track, he insists. "We're doing it," he said. "I'm confident. I know that we can do this on 14."

But what about beyond 14nm? Well, Intel's research group is exploring a host of technologies to take Moore's Law down to 10, seven, and even five nanometers. On one of his presentation slides, Bohr listed some of the technologies under study, including III-V and 3D transistors, graphene, extreme ultraviolet lithography, dense memory, materials synthesis, thinner interconnects, photonics, and nanowires.

When asked why carbon nanotubes weren't included that laundry list, since they had been on a similar slide last year, Bohr said, "We like to put the latest fads on that slide, so graphene's on that slide – that's the latest fad."

He also made it clear that a list was all he was prepared to provide. "I always get questions of 'Which ones are the promising ones?', and you can't pay me enough money to answer that question." ®

Bootnote

'OMG, I forgot the numbers!' (click to enlarge)

During his presentation, Bohr displayed a slide (right) that showed the similar slopes of defect-density improvements of 32nm and 22nm manufacturing processes, but which omitted any specific – and possibly incriminating – numbers on the defect-density y-axis. When asked if his omission of the numbers was intentional, he responded in mock shock: "Was it a mistake that I left the numbers out? Yes! Oh my goodness, how could I have done that? But, gee, time is up, so ... "