ARM tags GlobalFoundries for future chip tech
Doing the 20 nanometer two-step
ARM Holdings, the development company behind the ARM RISC collective that is expected to give x86 a run for its processor money, can't depend on one wafer baker partner, because with the exception of Intel, no one can. And so it is teaming up with GlobalFoundries on future chip tech, mirroring an existing deal with Taiwan Semiconductor Manufacturing Corp.
As El Reg previously reported, ARM Holdings inked a co-development partnership deal with TSMC Manufacturing Corp three weeks ago to extend their chip etching technology beyond 20-nanometer-sized transistor gates, extending an agreement signed in July 2010 that saw them collaborate on making chips with 20 nanometer features.
The partnership extension aims to bring sub-20 nanometer processes to bear on 64-bit ARMv8 processors, integrating TSMC's wafer baking with ARM Holding's Artisan tools. These tools are what the ARM collective use to modify ARM's ARMv7 and ARMv8 Cortex processor blueprints to optimize them for specific foundries and processes.
At the time, TSMC also said that it would be tuning its three-dimensional double-gate field-effect transistors (FinFETs) so they can be implemented with 64-bit ARMv8 processor designs.
As ordinary planar transistors have shrunk, they have become relatively poor switches, leaking current even when they are in the off position. With FinFET designs, the threshold voltage – the point at which the gate switches from one binary state to another – for the transistor is lower, so you get less leakage and lower voltage operation. As a bonus, the lower you drop the voltage on the chip, the lower the transistor switching gate delay, which can increase processing speed.
TSMC is still using planar transistor designs with a mix of enhanced high-K metal gate, strained silicon, and low-resistance copper ultra-low-K interconnects, but FinFETs are now expected in later process nodes.
As far as El Reg knows, TSMC's next chip process node is 14 nanometer, which is not expected to go into "risk production" (a kind of beta testing for chips) until 2014. TSMC is ramping its 28 nanometer processes now, but its slow pace has adversely impacted Advanced Micro Devices and Nvidia as well as others. TSMC started risk production of 20 nanometer parts at the end of last year for a ramp that will begin sometime in 2013.
You can see why ARM wants to have a second foundry partner for its RISC chip partners.
In a statement put out by ARM Holdings and GlobalFoundries, the two companies said that they have been collaborating for a number of years to line up the Artisan tools with the 28 nanometer processes that GlobalFoundries is running in its Fab 1 wafer baker in Dresden, Germany, and has run 20 nanometer test chips through Fab 8 in Malta, New York.
GlobalFoundries' Fab 8 plant in Malta, New York
The extended deal between ARM Holdings and GlobalFoundries covers Cortex processors at the 20 nanometer node using the low power manufacturing (LPM) variant of the process. The Mali graphics cards are going to be certified for GF's wafer bakers now, too.
For most nodes, there are versions tuned for various degrees of performance and power consumption, but the initial 20 nanometer node from GlobalFoundries is only available in LPM mode, which is aimed at processors used in smartphones, tablets, and other consumer devices. The 20 nanometer super high performance (SHP) process is not expected to be available from GlobalFoundries until 2014, and this process does not seem to be part of the deal.
Server variants of ARMv8 chips will likely lag the consumer devices, using more mature 40, 32, and 28 nanometer processes. ARM Holdings has already tuned its processor designs and tools for GlobalFoundries' 65 nanometer and 55 nanometer nodes, and the current 28 nanometer super low power (SLP) processes can be used to etch Cortex A9 processors, too.
Various RISC chip makers are using 40 nanometer processes today, including Oracle with the Sparc T4 and Calxeda's with its ARMv7-derived ESX-1000. Applied Micro Circuit's future ARMv8-derived X-Gene uses TSMC's 40 nanometer processes, and a kicker will be based on 28 nanometer transistor sizes.
GlobalFoundries says it will offer a range of transistor capabilities with the 20 nanometer LPM process, and that it will be able to deliver twice the gate density of its 28 nanometer processes while delivering about a 40 per cent performance boost for transistors.
It looks like GlobalFoundries will be adding FinFET 3D transistors after the 20 nanometer LPM process, and the two are working to make sure there is a transition from 20 nanometer LPM to whatever process GlobalFoundries uses to go 3D with its transistors.
In a separate but related announcement, GlobalFoundries says that it has begun construction on an additional 90,000 square feet of manufacturing capacity for Fab 8 in New York, with construction expected to be completed in December, bringing the site's capacity up to 300,000 square feet.
Fab 8 has a maximum of 2 million square feet of capacity, which is built out in modular fashion. This just extends Module 1, and it gives GlobalFoundries 60,000 wafer starts per month at the 28 nanometer node. Risk production is expected in Fab 8 by the end of this year, with volume production in early 2013.
This might be a good place to try to bake some 64-bit ARMv8 chips – provided you can second source from TSMC to hedge your wafer bets.
The funny bit in all this, of course, is that having two fab partners does not guarantee much these days. Look at AMD, which uses both TSMC and GlobalFoundries for its processors. It's disappointed with both of them right now. But how else is a chip designer supposed to hedge its bets? ®
COMMENTS
Re: The Virtual AI Terrain Team Solution to ITs Real Human and Surreal Practical Resource Problem
Ah, Man from Mars! It is good to see from you. But you are making less, or rather more, sense than usual. I think....
"Risk production is expected in Fab 8 by the end of this year, with volume production in early 2013."
Somebody call Tom Cruise, it's a Risky Business this chip production.
Re: The Virtual AI Terrain Team Solution to ITs Real Human and Surreal Practical Resource Problem
Ah, Man from Mars! It is good to see from you. But you are making less, or rather more, sense than usual. I think.... ... Timothy Prickett Morgan Posted Tuesday 14th August 2012 12:42 GMT
How wise to have all bases covered there, tpm, which might indicate to me that you are more aware of what is in the offing and betatesting especial and secret intelligence services to deftly engage, with or without officialdom in cyber security and information assurance positions in Blighty, or expose them all as being totally unfit and ill prepared for AI and NEUKlearer HyperRadioProActive Futures with ITs Greater IntelAIgent Games in Live Operational Virtual Environments. Or it might not be such an indicator, and that would be disappointing whenever it would render to El Reg an exclusive lead program to report on and share with a global audience.
And this would be the second shot across the bows of the Mary Celeste that is Francis Maude's and James Quinault's command to energise control and exercise virtual power, with the first broadside being this message to ocsia@cabinet-office.x.gsi.gov.uk
Methinks they be more Captains Pugwash than Admirals Nelson, though, in their roles. Although no one would more pleased than I to be proven wrong on those nautical scores.
The Virtual AI Terrain Team Solution to ITs Real Human and Surreal Practical Resource Problem
"But how else is a chip designer supposed to hedge its bets?"
Supplying novel smart applications for sophisticated machines with new processor chipped core designs in supplementary and proprietary in-house driver peripherals would deliver a guaranteed package which cannot fail because of sub-prime standard, third party virtual machine misuse.
Core processor manufacturing providing and running software programs intelligently designed in-house for hardware designing software, conveniently bypasses and eliminates the weak link which blights and corrupts and infects traditional practices and established systems with their revealing systemic self-destructive conflict glitches ….. that which inputs random instruction into systems infrastructure machinery for future core machine processing ……. the not so very smart programmer and equally intellectually challenged systems analyst.
Replace the faulty and always failing standard parts with new raw virgin models specifically chosen for upgraded super sophisticated sublimely stable units without prior memory and historical store taints/perverting and subverting programming preloding earlier designed to server and maintain/secure and retain a status quo position which has proven itself to be a costly colossal and monumentally destructive block on virtual machine and human progress.
That then delivers to a chip designer a limitless range of derivative options to explore in futures markets to render all bets, sure fire certs/guaranteed certainties. And it is easily provided to any and all who would currently be in need of it, or would wish for it to be supplied to guarantee their product supplies.
