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IBM's new Power7+ hotness - we peek through the veil

Saucy internet pictures reveal Big Blue secrets

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Power Seven PRIME - Sweet Mercy

I found two more images of Power processor roadmaps, and I will share them with you just so you can see what Big Blue is telling at least some of its customers. Here's the first one, which at least has the words Power8 and Power9 on it:

IBM Power roadmap, 2011 through 2020

IBM Power roadmap, 2011 through 2020

The next Power roadmap below doesn't really tell you much new except that IBM is internally calling the Power Gen2 processors that were announced last October Power7': Power Seven Prime. Never saw a prime symbol before added to a chip, but why not? IBM was adamant about not calling it Power7+, even though some of its own executives did so.

IBM's Power7 and Power 8 roadmap, circa October 2011

IBM's Power7 and Power 8 roadmap, circa October 2011

Here's another new one that I stumbled across that I think you will enjoy:

IBM Power chips over time

IBM Power server chips over time

This one shows the die shots of all the Power processors in the family - and to my amazement, also includes the Power7+ chip that has not been announced yet. A few things are immediately obvious from this chart. First, the Power4+, Power5+, and Power6+ chips were essentially unchanged compared to their Power4, Power5, and Power6 predecessors. And the Power6+ chips were a big disappointment since IBM missed the 45 nanometer shrink it had been expecting to add features to the chip and boost clock speeds. As you know, IBM didn't even call the Power6+ chips by the right name because it was trying to not talk about whatever issues the company was having with the 45 nanometer shrink.

Let's zoom in on those Power7 and Power7+ chips in that chart.

IBM Power7+ zoom

Power7+ gets topsies, Power7 get bottomsies

That's the Power7 on the bottom in its 45 nanometer process and the Power7+ on top in its 32 nanometer process. I flipped the orientation of the Power7 chip horizontally so the parts would map correctly. (You can see the original image of the Power7 chip I published back in February 2010 here, and you can see this is the same image as in this Power chip roadmap chart.)

Power7+ is a very different processor, not just a shrink, and that is probably why it is coming about six months later to market than IBM planned. (Power7 was due in May 2010 but was pulled ahead to February of that year because of Intel's "Westmere" Xeon 5600 launch.)

You can see that the Power7+ design wraps each core in L3 cache memory. Every nook and cranny of the chip is packed with L3. It looks like the L3 cache and chip core interconnect at the center horizontally in the chip is essentially the same. The local SMP links for the cores on the chips, which run along the top of the chip and halfway down the center middle and the right edge of the chip look largely unchanged, as do the remote SMP links and I/O links along the bottom edge and reaching up to the center middle. The two DDR3 memory controllers are on the outside edges, nestled between the SMP and I/O circuits.

For fun, I took an image of the Power7 core with its various elements and put it next to a zoom in on the rather low-resolution Power7+ chip image, and here's what it looks like when I tried to map out the chip elements to the Power7+ chip:

IBM Power7 and Power7+ cores

IBM Power7 and Power7+ cores

At the bottom of the chip is the 256 KB of L2 cache memory. Above that on the right are two load store units (LSU) and a condition register unit (CRU), a branch register unit (BRU), and instruction fetch unit (IFU). Each Power7 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache. The instruction scheduling unit, which is where the out-of-order execution in the chip gets handled is on the top right. On the top right are four double-precision vector math units, and in the top middle are the two fixed point units (FXU) and above that is the decimal fixed unit (DFU) that does two-digit money math. I took a stab at carving up the Power7+ core, and you can see, there is not that much different.

But, if you look carefully and take out the extra L3 cache memory wrapped around each core, you can see there is indeed some room at the top and the bottom of the chip for extra goodies. These must be the accelerators that IBM is talking about in the roadmap.

Some intrepid readers who keep track of the updates to the Linux kernel gave me a bit of help on what these might be. In this post at the Linux kernel drive database, we see that the Power7+ will have an n-nest cryptographic accelerator that supports the Advanced Encryption Standard (AES) encryption algorithm as well as the Secure Hash Algorithm-2 (SHA-2) functions developed by the National Security Agency in the United States. (Hash functions are used all over the place in code and microcode alike.) Here's another link at the Linux-Crypto site that talks about driver support for an on-chip AES accelerator. Intel's Xeon 5600, E5, and E7 processors support AES encryption and decryption, and Oracle's Sparc T4, announced last fall, supports both AES encryption and SHA-1 and SHA-2 hashing functions, among a slew of other encryption and hashing.

And here is yet another link that suggests there will be a random number generator etched onto the Power7+ processor. RNGs are also an important part of many applications, particularly in any kind of simulation that depends on, er, randomness, such as those in financial services or physics.

Undoubtedly more mysteries will be revealed about the Power7+ chip at the Hot Chips 24 conference by IBM. I am looking forward to it. ®

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