Intel rivals crash Hot Chips party with full-fat server silicon
Hey baby, wanna come upstairs and see my pipeline?
Drilling into Oracle's performance boasts
In any event, Oracle's Sparc processor roadmap from September 2011 said that the Sparc M4 chips were in test and would be used in machines spanning up to 64 sockets, just like the current Enterprise M9000 machines. Oracle is promising that the Sparc M4 processors would have 1.5 times the single-thread performance and six times the throughput performance of the M3s they replace, which has a lot of people scratching their heads.
Oracle's Solaris software gurus told El Reg last November that the M4s were based on a T series core, not a Fujitsu Sparc64 core, and would therefore be able to support Oracle's Logical Domain (LDom) hypervisor, which the Fujitsu Sparc64 chips cannot. This piece of data, if it turns out to be true, complicates the situation a little. It may simply not be true.
Just on raw oomph alone, if the Sparc64-X chip from Fujitsu was ramped up to 4.5GHz, which would certainly be possible with a 32 nanometer process if that is what Fujitsu is using, and kept two threads per core as was used in the Sparc64-VII+ chips, it fits the comparison between the M3 and M4 chips perfectly.
For the M3, you get a total of eight threads running at 3GHz, or a combined 24GHz of aggregate clocks, and for the M4 you get a total of 32 threads running at 4.5GHz, for a combined 144GHz of aggregate clocks. It could be, of course, that Oracle plans to take an 8-core or 16-core Sparc T5 chip, wrap some big SMP electronics and L3 cache around it, and crank the clocks up to the same range to get the same effect. This would effectively cut Fujitsu out of the high-end Oracle server business and make the two competitors, not partners.
You'll notice that Oracle is not showing off a Sparc M4 processor at Hot Chips. El Reg would guess that the Solaris guys got it wrong on what kind of core is in the M4 chip but have it right in that the Sparc M4, now called the Sparc64-X, does have the features on chip to support LDom portioning, and that adding this partitioning capability is one of the things that has taken so long to develop and made the Sparc64-VII+ look so long in the tooth.
Also on the server front, Intel will be showing off its "Sandy Bridge-EP" Xeon E5-2600 processor for two-socket boxes, which was announced back in March, and Applied Micro Circuits will also be showing off its 64-bit ARMv8-based X-Gene server processor, which the company divulged was in the works last fall and which could become a weapon in the upcoming x86-ARM server wars.
AMD will be talking about its "Jaguar" microprocessor, and Intel will be talking about its "Ivy Bridge" Core v3 and "Medfield" Atom Z2460 processors, which are used in PCs or mobile devices. It is interesting that AMD is not talking about the future server chips it has cooking based on its "Piledriver" cores and which will be compatible with the C32 and G34 sockets that its Opteron 4200 and 6200 chips plug into.
Techies from the University of Michigan will be showing off the Swizzle Switch, "a self-arbitrating high radix crossbar" for network-on-chip devices (PDF), which they think are better than mesh or flattened butterfly (FBFly) interconnects. They will also be trotting out the experimental Cenitp3de 3D stacked ARM chip complex that the university also presented at ISSCC earlier this year.
AMD will also be trotting out its "Trinity" Fusion APUs and HD7970 graphics processors, along with Intel providing some more specifics about its x64-based "Knights Corner" Many Integrated Core (MIC) coprocessors for supercomputing applications. Intel will also be gussying up its "Claremont" near threshold voltage 32-bit concept chip, which was also making the rounds at the International Solid-State Circuits Conference earlier this year. ®
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