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Intel rivals crash Hot Chips party with full-fat server silicon

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After hogging most of the oxygen in the server market with its new Xeon E3 and E5 processors this spring, Intel is going to get a little competition this summer as its rivals in the server racket trot out their upcoming server processors at the Hot Chips 24 symposium at Stanford University.

The Hot Chips event, which is hosted jointly by the IEEE and the ACM, runs from August 27 to 29 in Cupertino, and is one of two big events held each year when makers of CPUs for PCs, servers, and mobile devices, FPGAs, network processors as well as the latest chip manufacturing techniques such as die stacking and etching processes are trotted out for bragging rights. (The other event, of course, is the International Solid-State Circuits Conference hosted by the IEEE early in the year.)

This particular Hot Chips looks to be an interesting one, as a slew of new server and PC processors and possible adjuncts will be talked about in detail for the first time.

Wednesday is the big day for server chips, with IBM divulging the details of its Power7+ processor for its Power Systems line of servers. IBM has not said much about what the Power7+ chip will include, but as El Reg has previously reported, we know that IBM is planning to implement the Power7+ in a 32 nanometer process, giving it a fairly large shrink compared to the current 45 nanometer Power7 chips, which have eight cores and 32MB of on-chip embedded DRAM L3 cache memory.

El Reg has been able to get its hands on a few roadmaps, but all they show is that Power7+ will have higher clock speeds, a "very large cache", and unnamed accelerators on the chips. The Power7 chips first started coming to market in midrange boxes in early 2010, and are due for a refresh to make them more competitive with the latest Xeon and Opteron processors from Intel and Advanced Micro Devices.

IBM is also showing off what it calls its third-generation zNext processor for mainframes, which presumably means it is talking about the z12 kicker to the current z11 processors used in the System zEnterprise 114 and 196 mainframes.

These came out in July 2010, and they are also getting a little long in the tooth and are due for an upgrade. IBM is not saying much about what its plans are for zNext v3, but the current z11 chip has four cores on a die, is implemented in 45 nanometers, and runs at a top speed of 5.2GHz.

It seems likely that IBM will goose the clock speed a bit as part of a move to 32 nanometers with its chip etching processes on the z12 chips and will also add more L2 and L3 cache on the die. If IBM can boost the L3 cache enough, it may be able to do away with the off-chip L4 cache and controller and thereby simplify the components that go into its mainframes.

Oracle and Fujitsu are also rolling out their latest Sparc processors for servers at the Hot Chips 24 event. Oracle will be showing off its Sparc T5 processor, which will sport 16 cores and will have the necessary circuitry on those chips to glue up to eight of them together in a single system image in a NUMA configuration with one hop between processors. To get a one-hop NUMA connect with four sockets, you need three NUMA ports per chip, and this is something that you can do with the current Opteron 6200 and Xeon 4600 processors.

To do a one-hop link between eight sockets, you need seven ports coming out of each chip and a total of 56 ports, or you need some kind of funky crossbar switch that sits in the middle of all of the sockets – allowing each socket to hit the switch and link directly to another socket in the cluster. Oracle says that it is glueless, meaning it doesn't need any external chipsets to link the Sparc T5s together into a single system image.

Sometime partner and sometime rival Fujitsu appears to have at last committed itself to putting its future 16-core Sparc64-X processors into Unix machines, and will be showing this chip off at Hot Chips. Fujitsu is already shipping a 16-core Sparc64-IXfx processor in its PrimeHPC supercomputers, which are based on the same design as the K supercomputer, which uses eight-core Sparc64-VIIIfx processors.

Neither Oracle nor Fujitsu used a variant of the eight-core Sparc64-VIIIs in the Sparc Enterprise M machines, which seems a bit odd at first; they merely continued to sell the quad-core Sparc64-VII+ processors (called the M3 chips by Oracle). It seems likely that this choice was made because to get to 8 and 16 cores, Fujitsu had to radically gear down the clock speeds – from 3GHz with the Sparc64-VII+ down to 2GHz with the Sparc64-VIIIfx and down to 1.85GHz with the Sparc64-IXfx.

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