Nanodot memory smashes RAM, sets new speed record
Electro-optics boffins on a charge
Boffins in Taiwan and the University of California predict that nanoscale CMOS memory could soon be on its way after research showed nanodot memory operating 10 to 100 times faster than current RAM. The electro-optics researchers also emphasised that they had used materials that are compatible with mainstream integrated circuit technologies...
They built silicon nanodot memory by embedding silicon nanodots, just 3nm in width, in a layer of non-conducting material, and the covering it with a thin metallic layer. The base layer, dot and metal layer forms a set of transistors, with each dot acting as one bit. Its state is changed by having a green laser's light positioned on the part of the metal gate layer above a dot and firing a sub-millisecond burst of hot light which anneals that precise area of the metal layer and causes a metal-gate function there, positioned above an embedded silicon nanodot below.
A paper, Fast Programming Metal-Gate Si Quantum Dot Nonvolatile Memory Using Green Nanosecond Laser Spike Annealing, describing this was published in the American Institute of Physics’ (AIP) journal Applied Physics Letters. Its abstract reads:
The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 μs under low operating voltages of ± 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM.
Jia-Min Shieh, the co-author of the paper and a researcher at the National Nano Device Laboratories in Hsinchu, Taiwan, said: "The metal-gate structure is a mainstream technology on the path toward nanoscale complementary metal-oxide-semiconductor (CMOS) memory technology. Our system uses numerous, discrete silicon nanodots for charge storage and removal. These charges can enter (data write) and leave (data erase) the numerous discrete nanodots in a quick and simple way.
"The materials and the processes used for the devices are also compatible with current mainstream integrated circuit technologies. This technology not only meets the current CMOS process line, but can also be applied to other advanced-structure devices.”
In other words it shouldn't be too difficult to productise this technology. ®
Re: See... i knew i was stupid.
Nobody is stupid because they don't know something. Being stupid is being incapable or unwilling to learn.
See... i knew i was stupid.
Cheers for that. Today I have learned something that, granted, I will probably never use, but none the less, its good to know :)
Re: See... i knew i was stupid.
Conceding you are stupid (or that you do not know something) is a clear sign of intelligence.
Politicians never make such concessions
Re: maybe i'm stupid
why do you think we have fast caches for chips? Imagine the entire memory working at the speed of the CPU. That would be awesome.
At the moment, I have to think hard about cache friendly processing orders. Getting it wrong can incur a 10-fold speed penalty, easily. If have a set of for-loops to traverse an image, having the x-coordinate loop outside the y-coordinate loop is tens times slower than the reverse, because of the way images are stored (row by row). A step in x moves to the next element in memory (= cache hit with standard read-ahead), whereas a step in y steps a whole row of data further, yielding a cache miss.
Such simple cases are easily sorted out, but some image processing has data-driven processing orders, very frequently requiring odd memory jumps. In these cases getting rid of latency is a godsend. Also, think of multi-core: ensuring cache coherence is a pain. Older Cray machine had no cache, and the memory worked at the speed of the CPU. This is much simpler and yields much better parallelization.
Re: I dont quite see the progress here
My guess is that since the only mention of RAM is outside of the quote (which says non-volatile memory,) maybe El Reg got it wrong? It certainly does look more like a replacement for NAND (or possibly NOR) Flash rather than DRAM. A 1us p/e cycle would be a hell of an improvement over current NAND.
Also, +/- 7V doesn't seem remotely 'low' compared to any sort of modern volatile or non-volatile solid state memory. Maybe they mean it's low compared to alternatives that are currently in development? Or low compared to their last prototype? It certainly doesn't scream 'efficient operation on battery power,' which is kind of necessary for mobile use. Then again, DC-DC converters aren't all that bad these days.