5 ways to reduce advertising network latency

Prototypes of a new tiny, ultra low-power ARM-licensed processor will be demonstrated at an engineering conference in California next week. The chips are so small and energy efficient that they're aimed at wirelessly hooking up kitchen appliances, light bulbs and 'leccy meters to your network. And to the CIA.

Will this lead to sassy fridges ordering you to lose weight, based on your diet of crappy food, or intelligent heart-rate monitors advising you to stop reading about infuriatingly pointless shleb shenanigans in the news? Our fingers are crossed.

However, one group that certainly thinks it'll benefit massively from a surge in smart sensor proliferation is the world's spying organisations.

ARM Cortex-M0+ enter stage left

The concept of a smart home, or smart hospital ward, kitted out with tiny sensors is comfortably at least a decade old. By gluing microcontrollers (MCUs) to a bunch of detectors and wrapping them up in radio circuitry, you've suddenly got yourself intelligent little data broadcasters reporting back to a central decision-making storage hub.

There are plenty of tiny and very simple 8- and 16-bit microcontrollers out there to do this – but ARM thinks it can do better than everyone else in the low-power world and is determined to park its electric golf cart on the MCU industry's lawns. The Cambridge-based chip designer wants to take its powerful 32-bit architecture and drive it down to levels of power consumption enjoyed by more primitive 8-bit silicon, thus tempting engineers onto ARM's new Cortex-M0+ chips.

The M0+ follows the Cortex-M0 down the path of embedded simplicity. It uses ARM's compact Thumb instruction set; a rather barebones two-stage pipeline along which program code is fetched and executed; faster IO and flash memory access than before; an optional primitive memory protection unit that most manufacturers will leave out; and has added other speed and power tweaks to the design. There's no floating point unit although a ROM provided alongside the core can feature a maths library to provide routines for performing complicated calculations.

There's none of the huge cache, massive pipelines, multiprocessor interconnections, convoluted code execution reordering and other architectural bulk that weighs down Intel's powerhouses; the M0+ design starts off with just 12,000 gates. According to ARM CPU product manager Thomas Ensergueix, it's a completely new design started from scratch to push his company's platform further into the ultra low-power embedded world with minimal baggage.

These cores are expected to be wrapped up in flash and RAM in the order of scores of kilobytes, driven by a clock frequency of at most 50MHz, and draw 9 millionths of an amp per MHz on a 1.2V supply. The floor-plan area – the size the core will take up on a silicon die – is about a millimetre square, and it will cost manufacturers about 20 pence per core in royalties to ARM, we're told.

ARM's performance graph for the Cortex-M0+ compared to rival microcontroller cores. The graph represents just the code executing core and flash memory, using figures advertised by the rival manufacturers. The graph represents CoreMark benchmark performance per nano amp of current drawn.

Speaking to The Reg, Richard York, director of product marketing at ARM, said the 32-bit processor is aimed at embedded applications that need a bit more number-crunching power and perhaps more memory and interfaces, and better debugging support as embedded software complexity increases.

He argued that the amount of information that needs to be transferred can be reduced by using the extra processing oomph to massage raw sensor data in-core before transmitting it: this should further cut power requirements because broadcasting over the air is a significant current draw compared to what's consumed by the code-executing silicon gates.

Seasoned engineers told El Reg they are skeptical of this bold claim, arguing that once you throw in the communications software stack and protocols, the transmission overhead wipes out any power saving from sending 10 bytes instead of 200.

However in the case of a dumb microcontroller spraying a stream of, say, temperature readings to a larger decision-making computer, the benefit of replacing this component with a beefier chip that can turn around this data into a single packet to say "please turn off the heating" is more obvious. It's a delicate balancing act of power consumption in a technology scale where even the way a chip is wired up to the circuit board makes a significant difference.

York pointed towards Ember's ZigBee system-on-chips – which pack a Cortex-M3, 128KB of flash, 12KB of RAM and wireless personal networking circuitry – as an example of technology that can "cook data rather than leave it raw", maximising the efficiency of data transmission while maintaining portability. A hospital would prefer to strap tiny, wearable smart sensors to patients than have them tethered to heavy monitoring equipment, he said, as doctors "would rather have patients walking around than always strapped to a bed".

Email delivery: Hate phishing emails? You'll love DMARC