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Chip off the new block

Clock speeds on the initial batch of Xeon E5-2600 processors run from a low of 1.8GHz to a high of 3.3GHz, core counts range from as few as two and as high as eight. L3 cache runs from 5MB to 20MB, depending on the model. Here's how the Xeon E5-2600s stack up:

The Xeon E5-2600 processors

Feeds and speeds of the Xeon E5-2600s

All of the processors listed above support AES-NI encryption/decryption on the chip, as well as Virtualization Technology (VT) circuit-based assistance for hypervisors and Trusted Execution Technology (TXT) security.

The last two parts, the E5-2609 and E5-2603, do not support Turbo Boost (TB) overclocking or HyperThreading (HT), Intel's implementation of simultaneous multithreading. But all of the remaining models in the Xeon E5-2600 line do support HyperThreading, which carves each core into two virtual threads, and Turbo Boost, which adds anywhere from 200MHz to 900MHz to the clock speed of cores on the chip, depending on the model and the number of cores you have turned on when you hit the nitro. On eight-core chips, if you have all eight cores running, you get something between 200MHz and 500MHz, and shutting all the cores down except one will get you between a 500MHz and a 900MHz speed bump for that one core.

A platform, not just a chip

The prior generation of Xeon 5600 platforms – by which is meant the combination of processors and chipsets – was called "Tylersburg", perhaps after a dinky town in the middle of the Allegheny National Forest, and maybe the new "Romley" platform is named after a Colorado ghost town once known for mining.

Wherever it gets its name, Romley is the new two-socket server platform, and this is what it looks like:

Intel Romley platform diagram

Block diagram of the Romley server platform (click to enlarge)

Technically, this is the Romley-EP platform, and El Reg expects Intel to eventually offer a low-cost, two-socket server based on as-yet-unannounced "Sandy Bridge-EN" Xeon E5-2400 processors, as well as a four-socket Romley platform based on a forthcoming Xeon E5 variant. But Intel's top brass in the Data Center and Connected Systems Group are not talking about these other platforms on Tuesday, and would not confirm any of these details.

The Romley-EP platform puts two sockets on a system board and the Patsburg C600 chipset. Patsburg is basically a "Cougar Point" C200 chipset on steroids, and is technically a Platform Controller Hub (PCH) that has been optimized for server workloads. (The Intel 6 and C200 chipsets are used for PCs, workstations, and entry servers.) This PCH is basically the system clock for the motherboard, plus whatever southbridge functions that have not been absorbed onto the chip itself.

Intel Romley platform Patsburg chipset diagram

Intel's Patsburg chipset diagram (click to enlarge)

The Romley platform brings it all together, with two QPI links between the processors that allow close-to-ideal symmetric multiprocessing scaling on most workloads. The PCI Express 3.0 controllers on each Xeon E5-2600 socket have 40 lanes of bandwidth per socket, which can give you five x8 slots per socket. Then there's I/O bandwidth left over to give you a PCI-Express 2.0 x4 slot on one socket and a DMI2 slot on the other one.

The C600 chipset is a modified version of the C200 chipset with more storage and I/O options suited for enterprise systems. The chipset links to the Xeon E5-2600 processors through the DMI2 slot and can also make use of that PCI-Express 2.0 x4 slot as well.

You can hang a whole bunch of things off of this PCH, depending on what you activate in the chipset: 14 USB 2.0 serial ports, four or eight SAS ports running at 3Gb/sec, eight PCI-Express 2.0 slots, a plain-old PCI slot, four SATA ports running at 3Gb/sec or two SATA ports running at 6Gb/sec. There are also ports for various kinds of other storage and peripheral devices.

El Reg will be digging into the details on the new Xeon E5-2600 processors in terms of performance and pricing, as well as looking at how server makers deploy these chips and chipsets in their machines. Stay tuned. ®

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Latest Comments

Re: Is this really progress? I seem to have missed it.

Moving functionality on-chip decreases latency and increases throughput and performance. Just not raw CPU crunching performance perhaps. But even CPU crunching benefits from lower latency memory accesses, the biggest advance there for Intel was with QPI.

This chip with on-chip PCIe gen3 controllers (think 40G Ethernet and beyond) will be great for network processing. Indeed this is one of Intel's focuses. See http://www.intel.com/content/www/us/en/communications/global-communications-network.html

Intel is not designing chips just for your desktop but for a lot of diverse use cases.

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Tweaked for bloatware performance ?

Perhaps with the exception of floating point performance, it seems unlikely that highly tuned programs will run very much faster on this. If on the other hand you are running a crapload of bloatware, all of the listed performance tweaks should translate into higher overall performance.

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(Written by Reg staff)

Performance coming....

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