Regcast training : Hyper-V 3.0, VM high availability and disaster recovery

It’s getting increasingly difficult to pack enough processing power into mobile phone form factors, so US researchers are proposing a new scheme: seriously over-spec the processors, but only use their power when it’s needed.

The research paper, authored by scientists from the Universities of Pennsylvania and Michigan, suggests a scheme called “computational sprinting” – build mobile chips not with a couple of cores working hard all the time, but with as many as 16 cores, most of which are idle unless they’re needed.

For much of the history of the integrated circuit, smaller geometries that allow more transistors to be packed into less space are accompanied with lower operating voltage, which helps designers cope with the job of getting rid of the heat generated by all those extra transistors.

Without that, power density increases from one generation of processor to the next and in mobile devices, power (and cooling) rather than chip real estate becomes the barrier to higher performance.

Hence the “computational sprinting” described by the researchers. Their analysis looks at a system that spends most of its time operating a single core with 1W peak power, since most smartphones spend most of their time doing not very much. The system could, however, “burst up” to use all of its cores when necessary.

This, the paper states, is representative of the user experience with smart phones: “short bursts of intense computation punctuated by long idle periods waiting for user input” (El Reg: sounds like a quotation about war, for which I can’t find a good citation right now).

The whole chip could be fired up for the computationally-intensive task, even though this would momentarily exceed the power budget and heat dissipation capabilities of the device, because there’s a time lag between powering-up the processor cores and the extra heat generated. This “thermal capacitance” (also used by burst systems like Intel’s Turbo Boost technology), combined with usually “dark” silicon, could “result in an intense sprint with the potential to provide an order of magnitude improvement in responsiveness”, the authors state.

The paper, by Arun Raghavan and Milo Martin (University of Pennsylvania), and the University of Michigan’s Yixin Luo, Anuj Chandawalla, Marios Papaefthymiou, Kevin Pipe, Thomas Wenisch, was prepared for the 18th Symposium on High Performance Computer Architecture, and is available here. ®

Regcast training : Hyper-V 3.0, VM high availability and disaster recovery