Chip boffins demo 22-nanometer maskless wafer-baking
A possible savior when Moore's Law hits the light wall
An international consortium of chip boffins has demonstrated a maskless wafer-baking technology that they say "meets the industry requirement" for next-generation 14- and 10-nanometer process nodes.
Current chip-manufacturing lithography uses masks to guide light onto chip wafers in order to etch a chip's features. However, as process sizes dip down to 20nm and below, doubling up on masks begins to become necessary – an expensive proposition.
At last November's 40th birthday party for the pioneering Intel 4004 microprocesser, The Reg asked Intel Labs' director of microprocessor technology research Shekhar Borkar if multiple masks might be the solution to ever-tinier process nodes. He told us, that, yes, it would be possible, but that adding masks increases both complexity and cost.
One solution would be to eliminate lithography masks altogether, and etch the chips directly with guided electron beams – think old-style cathode-ray tubes, but with much smaller, much more tightly controlled beams.
That's exactly what MAPPER Lithography of Delft, The Netherlands, has done in conjunction with CEA-Leti, the French Research and Technology Institute, in a project dubbed IMAGINE, an effort joined by such industry heavyweights as TSMC and STMicroelectronics, as well as Nissan Chemical, TOK, Dow Chemical, JSR Micro, Synopsys, Mentor Graphics, Sokudo, Tokyo Electron, and Aselta Nanographics.
MAPPER's breakthrough has been to demonstrate a chip-etching technology that uses 10,000 precisely directed electron beams that etch features directly onto a wafer. As explained in their announcement, "The major achievement has been obtained in resolution: 22nm dense lines and spaces and 22nm dense contact holes in positive chemically amplified resist have been successfully resolved."
Don't expect this technology to supplant mask-based photolithography any time soon, however. This year, MAPPER plans to introduce a "pre-production" version of its Matrix system that will have a slo-mo throughput of one wafer per hour, and which the company plans to scale up to 10 wafers per hour.
"Given the great results we have obtained at CEA-Leti thus far," MAPPER CEO Bert Jan Kampherbeek said in his company's announcement, "we are proud to announce that one of the first Matrix systems will be installed at CEA-Leti to enable the continuation of the IMAGINE programme."
The Matrix system will indeed be slow – but so are current versions of one of traditional chip lithography's waiting-in-the-wings saviors, extreme ultraviolet (EUV) lithography "To have a fab running economically, you need to build about two to three hundred wafers an hour," the head of ARM's Physical IP Division Simon Segars said at last year's Hot Chips conference. "EUV machines today can do about five."
The jury remains out on what will take over from conventional lithography when it hits the multi-mask wall – but seeing as how even EUV will require expensive masks, the maskless Matrix system and its follow-ons just became a viable contender. ®
e-beam lithography has lots of benefits, but it is extremely slow. This technique increases its speed by a factor of 10,000 by using parallel beams.
The article points out one advantage: you no longer need to create a mask, and the cost of the mask is drives the cost of the photolithographic process. Masks have become extremely challenging as feature sizes dropped below the wavelength of the light used for the photolithography: the mask is no longer a simple reproduction of the shape of the desire result. Rather, the mask (rather, the masks, since "double-patterning" is needed) have funny shapes that cause the light to interact with the surface based on the rules of optics,and not all desired results have corresponding masks.
But there is another consequence that is even more important: A mask is so expensive that you must produce a huge number of parts to amortize the mask cost. For E-beam, you can spefiy the exact result you want, and the beam can produce that exact result. But even more importantly, there is essentially no penalty for creating multiple different kinds of devices on the same wafer. This completely changes the economics for creating experimental devices and for small production runs of ASICS, and it allows the industry to re-open the idea of wafer-scale integration.
E-beam failed because is was too slow, and it lost ground to photolithography as the wafers got bigger and the feature sizes got smaller. But suddenly we have parallel e-beams, which conceptually increase the speed by number of parallel beams (currently 10,000.) But if 10,000 now, why not 1,000,000 in the future? We get to the point where a specialty fab could produce a single instance of an experimental custom device for not too much extra money, and suddenly we can create a small quantity of ASICs for $100 apiece.
Small runs become much more interesting this way. Ultimately, one might envisage chip making to be commoditized like 3D printing is becoming a commodity. One off parts are becoming affordable (see LOHAN). Imagine designing your own ASIC chip from scratch rather than going the FPGA route. Design a schematic, send it off, have a wafer-full made, mounted and sent to you.
Far fetched now, but maybe some day.
What do you mean "a man can dream"? A man should dream!
I'm pretty sure
he was talking about the operation of the finished chip, not the production method.
This idea is far from new.
However, in the past electron-beam 'masking' was always considered much slower hence more expensive. It'll be interesting to see how it scales up now that's it's become forced on the industry.
Quantum tunneling doesn't necessarily manifest
in the equipment used to etch a pattern on silicon. Quantum tunnelling is how the uncertainty principle manifests as electrons travel along ever-smaller circuits. As you shrink circuits and the overall energy levels approach Planck scale (which might be measured in terms of energy gaps or distance) then it causes electrons to apparently "teleport" at random, so smaller circuits introduce quantum glitches.
If you're talking about the actual process by which circuits are etched, however, you're probably talking about very high energy beams (x-ray lithography or, in this case, an electromagnetically accelerated electron beam) then the energy of the photon (x-ray) or electron (CRT-like accelerator) can be ramped up to a level where they're well in excess of the Planck-scale energy levels, so won't be as affected by the uncertainty principle.
There are still problems, though. Even x-ray lithography (higher energies relative to UV) mightn't have enough energy to cast a clean shadow against the mask--hence (I take it) the need for multiple masks and x-ray sources. As for CRT, aiming is still hard at high energies due to the need to have a very high frequency circuit for steering the electron beam. Aiming has been a problem with CRTs since the beginning. The traditional solution (to get the electron to hit the right pixel) is to have a charged mesh close to the target which helps to focus electrons that are slightly off-target or absorb those that are more wildly off. Higher-energy electron beams probably do something similar.
The designers of these kinds of etching hardware still have to worry about the uncertainty principle as they get to ever-smaller scales, but the physical description of their problems manifests more as wave/particle duality (inability to cast hard shadows due to edges causing a diffusion/diffraction of the beam) than quantum tunnelling per se ("teleporting" low-energy electrons in a circuit). At least, that's how I understand it...