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New chippery on parade at ISSCC

CPU and memory makers strut their stuff

7 Elements of Radically Simple OS Migration

The new year in IT always begins around now, when the IEEE puts out the advance program for the International Solid State Circuits Conference, which takes place in San Francisco in February. This time around, it runs from February 19 through 23, and while there are not a large number of server-class processors coming out, there are some very interesting system-on-chip and memory technologies that chip makers will be showing off at the upcoming 2012 event.

First out of the gate will be Intel with a preview of the "Ivy Bridge" processors for PCs, which are made in its new 22 nanometer Tri-Gate process and which will cram a multicore CPU and a GPU onto the same sliver of silicon. Intel will also be showing off a new dual-core Atom processor implemented in its current and well-established 32 nanometer processes sporting on-chip Wi-Fi networking. This is presumably the "Cedar Trail" family of Atom processors that were originally expected around September, then November, and now sometime next year, according to the rumor mill. Intel will also be showing off a 32-bit x86 chip that has an operating range of between 280 millivolts to 1.2 volts that is implemented in its 32 nanometer processes.

Oracle will be on hand to talk about the eight-core Sparc T4 processor that was announced back at the end of September and that just started shipping in systems back in November. Oracle might slip a bit and talk about the future Sparc T5 processor, which will be socket-compatible with the Sparc T4 processor and which will ship by late 2012. Then again, Oracle doesn't want to screw up Sparc T4 system sales, so maybe it won't say anything. Especially considering that the Sparc T5 will have 16 cores running at around 3GHz or so and scale up to eight sockets in a single system – yielding about 2.5 times the aggregate oomph on thread-happy workloads like databases and middleware.

IBM is not saying anything about its future Power7+ or Power8 processors for its Unix and proprietary systems. But Big Blue will be showing off a prototype 3D system-on-chip design that will use through silicon via (TSV) technology that it perfected with Micron Technology for hybrid cube memory. IBM will be demonstrating that the techniques that can be used to stack up DRAM chips and lash them together into a parallel memory cluster (well, that is what HMC memory is, more or less) can be used to link embedded DRAM to processor cores. Such technology will be needed to make more powerful and energy-efficient parallel systems.

Researchers at the Georgia Institute of Technology, Korea Advanced Institute of Science and Technology, and Amkor Technology will be showing off a similar stacked chip called 3D-MAPS, which is a massively parallel processor with stacked memory. In this case, the chip in question has 64 cores running at mere 277MHz and 256KB of SRAM memory mated to it. This is a tiny chip in terms of raw chip performance, but it delivers 64GB/sec of memory bandwidth and only consumes 5 watts of juice, and on memory-intensive workloads with a certain degree of parallelism, 3D-MAPS could scream. The next generation 3D-MAPS chip will have two logic tiers with a total of 128 cores and three DRAM tiers instead of one SRAM tier for memory.

The University of Michigan will be stacking up chips, too, with its Centip3De project, which will put 64 ARM Cortex-M3 embedded processors into a cube. The Wolverines have been talking about (PDF) a seven-layer 3D chip that has 128 Cortex-M3 cores and 256MB of stacked DRAM all glued together, so this appears to be a chip off the old block.

Advanced Micro Devices will be showing off a "resonant clock design" for a 64-bit x86-processor towards the end of the day, and clearly there will be a need for some coffee during that one. Fudan University of China will be showing off a 16-core, 320 milliwatt, 800MHz processor it has cooked up with message passing and shared-memory inter-core communications – all cooked up in an ancient and cheap 65 nanometer process. Cavium will be showing off its latest 32-core MIPS-based processors, which sport network accelerators and which are sold under the Octeon II brand. Fujitsu will be there to show off its current K massively parallel supercomputer, powered by the eight-core Sparc64-VIIfx processor and currently the most powerful super in the world.

Hynix Semiconductor and Samsung Electronics will be showing off their respective 2Gbit and 4Gbit DDR4 SDRAM memory chips, which will eventually make their way into PCs and servers. ®

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