Intel, Micron double single-chip flash capacity
How does a speedy 128Gb grab you?
Intel and Micron, through their IM Flash Technologies (IMFT) joint venture, have announced the development of what they call the world's first 20-nanometer, 128-gigabit, multilevel-cell flash-memory chip, and that they have begun "mass production" of their 20nm 64Gb chip.
"Through the utilization of planar cell structure and Hi-K/Metal gate stack, IMFT continues to advance the technological capabilities of our NAND flash memory solutions to enable exciting new products, services and form factors," said Intel's Non-Volatile Memory Solutions Group general manager Rob Crooke in a statement.
Intel says that one-terabit densities can be achieved in "a single fingertip-size package" consisting of eight of the new parts – a claim, we assume, that depends upon how big your hand is and which finger you're talking about.
There's an elegance to NAND chips that would please the most austere 1960s minimalist artist
IMFT's target market is, of course, the world of ever-shrinking mobile devices and the cloudy servers that feed them.
"As portable devices get smaller and sleeker, and server demands increase," said Micron's NAND Solutions Group VP Glern Hawk, "our customers look to Micron for innovative new storage technologies and system solutions that meet these challenges."
The IMFT's 20nm 64Gb part is ramping to mass production this month, and the 128Gb part will be sampling to customers in January, with mass production scheduled for the first half of next year. ®
That is almost small enough for MicroSDXC!
What with HD's gauging prices and flash prices dropping (which in many ways you can thank Apple for in some ways - there I said it). Well I can only see some nice consumer priced and usable flash storage comming to market, along with the reduced heat and power usage as well as reducing the I/O gap to memory/CPU. This can only be happier times. Once we get optical interconnects if only due to the fact that glass/plastic is cheaper than metal. Then I'll be even happier than I am now.
Good times ahead.
"Intel says that one-terabit densities can be achieved in "a single fingertip-size package" consisting of eight of the new parts"
Question is, does this mean a flash chip that hosts 8 dies (as opposed to the practice of 4 dies in current 512GB+ drives)? Surely, since 4 dies per chip causes interleaving bottlenecks to the dies, dropping 8 dies on a chip could cause similar (worse?) issues if the controller isn't striping the data efficiently? Perhaps an upgrade to channels from the controller is in order...
"although at 333 megatransfers per second (MT/s) it doesn't hit that standard's minimum speed of 400 MT/s."
400 MT/s is the *maximum* supported transfer rate on the NV-DDR2 interface which was added to ONFI 3.0 (versus 200 MT/s on the older NV-DDR one).