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IBM unveils high-capacity, high-speed storage chippery

'Racetrack memory' off to the races


IBM has scored a blow in the high-stakes prizefight for the title of next-generation non-volatile memory technology, revealing a prototype "racetrack memory" chip baked using the same silicon fab technologies as run-of-the-mill chippery.

Racetrack memory, for those of you who haven't been scoring at home, is competing with such technologies as phase-change memory (PCM), triple-level cell (TLC) NAND, magnetoresistive random-access memory (MRAM) – even IBM's fading MEMS-based (and trés bizarre) Millipede effort.

The goal of IBM's racetrack memory research has been to fabricate a storage technology that marries hard-drive capacities with flash-memory speeds and knock-aroundability. In a nutshell, racetrack memeory involves sending magnetic "stripes" through nanowires, written by imparting spin to the electrons and read by an analog to a hard drive's read head – except that the racetrack memory's read head detects the edges of the magnetic stripes rather than their polarity.

IBM has been working on racetrack technology since the middle of the last decade, first exhibiting a working prototype in 2008. At that time, IBM's marketing minds produced a decidedly gee-whiz, non-technical video explaining the concept behind the technology:

The breakthrough announced this Monday at the IEEE International Electron Devices Meeting (IEDM) in Washington DC, is that Big Blue has placed racetrack-memory nanowires and their support circuitry onto a chip built using standard fabrication tools – a necessary step toward productization and commercialization.

The IBM chip's nanowires are formed by depositing a nickel-iron coating on top of silicon, then etching it into separate wires using standard chip-baking photolithography. Each nanowire is about 10 micrometers long, 150 nanometers wide, and 20 nanometers, according to MIT's Technology Review.

Dafiné Ravelosona of France's Institute of Fundamental Electronics, who is also working on racetrack memory tech, told Technology Review that the IBM chip is "a nice demonstration," but since it can only move one bit at a time on the wire, not a series of bits, much more work needs to be done.

IBM's racetrack-memory daddy, Stuart Parkin, responded to Ravelosona by saying "We're focusing on exactly this question." In specific, Parkin and his team are looking at materials that hold domains more tightly, and thus can more easily contain multiple stripes on the same nanowire.

Exactly when the multi-stripe problem will be solved is not known, but don't expect racetrack memory to appear in your Ultrabook anytime soon. While IBM continues to work on it, of course, work will also continue on its competitors in the battle for the next-gen nonvolatile memory crown. ®

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