Report: SAS controller bug holding up Xeon E5 launch
A different bug this time?
Everyone was expecting for Intel to launch the "Sandy Bridge-EP" Xeon E5 processors back in September for delivery in the fourth quarter. Butfor reasons that Intel has never explained – much less admitted that this was the original launch schedule – the E5 processor and its related "Patsburg" chipset has been pushed out to an "early 2012" launch.
Unless you were a supercomputer or hyperscale cloud computing customer willing to take the machines under a non-disclosure agreement, that is. Then, if you play your cards right, you could get access to the Xeon E5 chips.
A report in DigiTimes says that the E5 processors and their "Romley" platforms, as Intel calls the combination of its processors and chipsets, will come out in the first week of March. Citing unnamed sources in the server supply chain, the publication said that the reason the chips did not launch back in September was because of a bug of some sort in the pairing of the Patsburg C600 chipset and the Xeon E5 processor, which is aimed at two socket servers.
You will recall that the launch of the "Sandy Bridge-DT" Xeon E3-1200 processor for single-socket servers was delayed back in January by a bug in the SAS controller used in the "Cougar Point" Intel 6 chipset, used with Core i5 and i7 variants of the Sandy Bridge processors. The Intel 6 chipset implements four 3Gb/sec SATA ports as well as two 6Gb/sec SATA ports, and only the 3Gb/sec ports were affected by the flaw found in January.
OEMs did some testing on the laptop versions of these chipsets and found high bit-error rates on the legacy SATA ports. Intel did its own tests and found that there was a 5 per cent chance a laptop would fail under normal usage with the Sandy Bridge-Cougar Point combo, over the course of three years, and a heavily used machine in a hot environment might see a failure rate as high as 15 per cent.
With the desktop chipset delayed, Intel had to double-check the C200 server variant of the Cougar Point chipset before launching later in 2011. Intel had to shell out $300m to cover the costs of manufacturing the faulty PC versions of the Cougar Point chipsets, and took another $700m hit to replace motherboards that OEMs made that had the faulty parts, but because it delayed the launch of the Xeon E3 chips, it didn't take such a hit.
If there is a bug in the SAS controller implemented in the Patsburg chipset when used in conjunction with the Xeon E5s, by delaying the manufacturing and launch of the chipsets and boards, Intel could keep its books from being hit a second time by the SAS bug.
As you might expect, Intel dodged questions about whether there was a bug in the SAS controller in the Patsburg chipset, or any other bug relating to the Xeon E5, as it has been doing since September.
"We are not commenting on rumors and speculations about unannounced products," an Intel spokesman told El Reg via email in response to inquiries. "We are very happy that everyone is so eager to get their hands on our new Intel Xeon E5 processors and based on SC11 published HPC benchmarks results it is clear that this will be extremely high performing platform."
As far as El Reg knows, the Romley platforms will support a variety of SAS and SATA ports, depending on the Patsburg chipset chosen. The C600-A has four 6Gb/sec SATA ports, the C600-B adds 6Gb/sec SAS support, the C600-D adds for more SATA ports or two more SAS ports for a maximum of eight ports, and the C600-T adds for software-based RAID 5 data striping across the SATA drives. Interestingly, the Patsburg chipset does not support legacy 3Gb/sec SATA ports.
"In the more than two decades that I have been watching Intel, the company never makes the same mistake twice," Nathan Brookwood, principal analyst at chip watcher Insight 64, told El Reg. "If there is a problem with the SAS controller, it is something different."
And with Advanced Micro Devices' Opteron 4200 and 6200 processors not exactly putting a lot of pressure on Intel – at least not like AMD did back in 2003 through 2007 – Intel can afford to take the time to get the Romley platform right.
The one thing that people were murmuring about back at Intel Developer Forum in September, and the SC11 supercomputing conference earlier this month, is that whatever is holding up the Xeon E5 launch might have to do with performance issues on the on-chip PCI-Express 3.0 controllers that the processors sport. This is the first on-chip implementation of the PCI-Express Gen 3 controller among any chip maker, and there are bound to be issues here, too, between processors, chipsets, and adapter cards (such as 56Gb/sec FDR InfiniBand cards, which require PCI-Express Gen 3) with so many technologies all changing at the same time.
Intel refused to comment on the matter at both IDF and SC11 and stood steadfast to its position that it never promised the Xeon E5s this year, that it will ship lots of them this year despite them not being formally launched, and that everything is hunky dory. ®
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"If there is a bug in the SAS controller implemented in the Patsburg chipset when used in conjunction with the Xeon E5s, by delaying the manufacturing and launch of the chipsets and boards, Intel could keep its books from being hit a second time by the SAS bug."
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