Oracle revs up Sparc, speeds up roadmap
Years to go before Larry dumps x86 and Sparc64
The HotThreads era
"The major nodes of T4 are available now," Fowler said, "and it's faster than what we said publicly. It's much faster that what we said publicly. And where we are going in the Sparc roadmap is very active."
Being someone who has garbled more than a few sentences in my life, I will cut him slack and simply point out that I know what he meant. "We are very actively in test and have systems up and running along the next line of systems," he continued. "We've made some modifications to the roadmap. We've pulled in some of the upgrades to the T Series, and added another upgrade to the T Series, which we are going to go into some detail about in a future announcement."
So here's the revised Sparc processor roadmap:
As you can see when comparing the roadmaps, the new S3 cores are delivering a 5X performance increase on single-threaded work compared to the 3X that was promised, partly because of the out-of-order execution on the new S3 core, but also because of the larger L3 caches and the 3GHz clock speed of the top-bin Sparc T4 parts.
The CoolThreads era, where 1GHz to 1.65GHz clocks were the design point, is over. We are now in the HotThreads era.
The interesting change in the revised roadmap is that the kicker to the T Series chips, the Sparc T5, which was slated for delivery in early 2013 on last year's roadmap, has now been pulled into 2012.
On the old roadmap, this Sparc T5 chip was supposed to have three times the throughput as the Sparc T5 and the same single-thread (what Oracle calls "single strand") performance; it is aimed at machines with from one to eight Sparc T processor sockets. This chip looks like the "Cascade Falls" processor that Sun had on the roadmap with 16 of the S3 cores, which were called "VT" cores back in late 2009 when this roadmap came out:
On the new and improved Oracle Sparc roadmap, the Sparc T5 is now slated to deliver only 2.5X the throughput, not 3X, but it is coming to market considerably early –my guess is about six months, but it is hard to say from these roadmaps. That's not a big dip in performance and having it to market earlier on Taiwan Semiconductor Manufacturing Corp's 28 nanometer processes is more important than an extra 20 per cent oomph.
Time-to-market is everything for Oracle now, particularly if it wants to protect its Sparc base against the onslaught of IBM's Power Systems and the hordes of x86 vendors peddling Linux and Windows as an alternative to Sparc/Solaris.
The removal of support for future Oracle software releases on Itanium pretty much puts HP-UX in limbo, and if the situation gets bad enough and if IBM hasn't actually nailed down support contracts with Oracle, then it is reasonable to assume that Power gets unplugged next.
In any event, the Sparc T5 processors will go into testing in October. A kicker for the Fujitsu Sparc64-VII+ processors, with six times the throughput and 1.5 times the single-thread performance, is already in test. It is very likely that this is a variant of the eight-core "Venus" Sparc64-VIIIfx processor that is at the heart of the K supercomputer built for the Japanese government by Fujitsu. Those Sparc64-VIIIfx chips run at 2GHz – not very fast.
The latest Sparc64-VII+ processors used in the Sparc Enterprise M midrange and big iron boxes, announced in December 2010, top out at 3GHz with 12MB of L2 cache, 64KB of L1 data cache, and 64KB of L1 instruction cache.
The Sparc64-VIIIfx has L1 caches that are only 32KB each and only 5MB of L2 cache, but it moves two DDR3 main memory controllers onto the chip and doubles up the core count to eight. If you pushed the clock speeds up to 3.5GHz on this eight-core chip, you'd only get about a factor of 2.3 more performance out of the Sparc64-VIIIfx compared to the current Sparc64-VII+ chips. So it looks like Fujitsu is doing something different with whatever this future Sparc Enterprise M server chip.
Perhaps Fujitsu is plunking a fat L3 cache on the chip as well as cranking the clocks and doubling the cores?
Whatever is going on, Fowler said that a follow-on Sparc64 is on track for late 2013 or early 2014, and in that same timeframe Oracle has added a new Sparc T Series chip – we'll call it the Sparc T6 just so we can keep it straight – that will have more single-threaded performance and presumably faster clocks. This Sparc T6 will work in machines with one to eight processor sockets, and that is all that Oracle has said about it so far.
Beyond that, the future Sparc processor which will have 64 sockets with a total of 16,384 threads, will support 64TB of main memory, is on track for delivery in late 2014 or early 2015. This future Sparc, which significantly is called neither an M Series or a T Series chip in the presentations, is having its feature set defined now, says Fowler.