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Deep inside Intel's 'Ivy Bridge' chip

A really small Sandy Bridge. And more

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IDF 2011 Intel's next-generation "Ivy Bridge" chips will include a host of improvements, including integrated graphics that the company claims will narrow the lead now held by AMD's Fusion APUs.

"I expect that that gap, from everything that I've seen, is closing fast," Intel's director of graphics architecture Tom Piazza told an Ivy Bridge confab on Tuesday at the Intel Developer Forum (IDF), when he was asked if Intel was closing the performance gap with its competition – presumably AMD.

"I don't see any reason why it won't close all the way," he confidently continued, "and maybe you'll be asking the other guys that question in a year or two."

Improved graphics performance is not the only architectural improvement in Ivy Bridge over Intel's current "Sandy Bridge" chips. Also new, said Ivy Bridge interconnect and integration engineer Varghese George at the same session, are support for low-power DDR3L memory, dynamic (no reboot) overclocking control of both the compute and graphics cores, power-management improvements, security enhancements to guard against escalation of privilege attacks, and more.

Intel Ivy Bridge

Ivy Bridge is not just a shrink of Sandy Bridge from 32nm to 22nm ...

Intel Ivy Bridge

... it includes improvements to a host of architectural improvements, as well

Such a significant redesign is unusual in Intel's "tick-tock" chip-release cadence, in which a tick in a process shrink – say, from 32nm to 22nm – and a tock is a new architecture. During his IDF keynote on Wednesday, Intel's PC client honcho Mooly Eden referred to Ivy Bridge as "a tick-plus" – a scaled-down version of Sandy Bridge, but with its own architectural improvements.

Eden focused on one of those improvements, a power-saving enhancement called power-aware interupt routing, or PAIR, which intelligently sends interrupts to cores that are already up and running, rather than to those that have been powered down and are comfortably asleep.

Accessories and external devices continually send interrupts to a CPU to check on what's what. USB, for example sends around three thousand interrupts per second – and if a core is asleep, it must wake up to handle that interrupt before it can go back to sleep.

"And the minute it wakes up, it starts consuming power," Eden explained, "and it tries to go back to sleep and [the interrupt] wakes it up – and you know how annoying it is when you wake up and sleep and wake up and sleep."

Without PAIR, Mooley said, each of USB's 3,000 interrupts per second are sent to core 0 – and if core 0 is asleep, USB wakes it up, which wastes power. Simply put, PAIR routes interrupts to a core that's already awake, thus saving power. A small amount, to be sure, but in the world of power management, many small amounts can add up to significant power savings.

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