IBM, 3M glue chips into silicon skyscrapers
Build tower of Power
IBM and adhesive maker 3M are teaming up to cook up the packaging goo that will be needed to stack up chips into 3D arrays.
There is a growing consensus in the computer industry that more compact and three dimensional packaging of chips is necessary to keep increasing the performance and reducing the power draw of everything from smartphones to supercomputers. The industry has thus far reduced power consumption and the physical size of chips by shrinking the lithographic processes used to etch the circuits on the chips, but at some point in the future we will start reaching approaching the physical limits of these processes.
So the idea is to take components that are often separate on a system – processors, main memory, networking and other peripherals – and etch them all onto chips and then stack them up in a 3D array, rather than solder them onto a motherboard and wire them together with metal stripes in a 2D array. By going 3D, the wires between components can not only be shortened - cutting the time those components need to exchange signals and potentially requiring less energy to send a signal.
IBM is an expert in chip packaging, which you have to be to create the monster multichip modules (MCMs) at the heart of a mainframe, as well as being one of the major foundries in the world. 3M also has a business unit that sells tapes and adhesives for electronics manufacturers, flexible circuit boards, and chemicals and abrasives used in the manufacturing and cutting of chips.
Building a silicon skyscraper with chips and goo
The initial plan from IBM and 3M is to come up with an adhesive that will not only link chips electronically to each other, but also dissipate the heat generated during operation to the outer packaging. Conceptually, here's what it looks like:
3D chip goo needs to hold tight and move heat
"Today's chips, including those containing 3D transistors, are in fact 2D chips that are still very flat structures," explained Bernie Meyerson, a vice president of IBM Research, in a statement announcing the partnership between Big Blue and 3M.
"Our scientists are aiming to develop materials that will allow us to package tremendous amounts of computing power into a new form factor – a silicon skyscraper. We believe we can advance the state-of-art in packaging, and create a new class of semiconductors that offer more speed and capabilities while they keep power usage low – key requirements for many manufacturers, especially for makers of tablets and smartphones."
The initial plan is to come up with a way to stack up as many as 100 chips into a tower of computing power. Over the long haul IBM wants to be able to bond stacks of complete wafers together, bonding hundreds of processors at a time.
Neither IBM nor 3M let slip the timing of delivery for 3D chip packaging techniques based on the new adhesives in their announcement, but a source at IBM tells El Reg that Big Blue has been using an adhesive in 3D analog/digital converter chips and based on that experience and with the help of 3M, IBM believes that it can get the process to scale across larger chips and taller stacks. The plan, says the IBM source, is to get it into production around the end of 2013.
IBM and 3M did not say if the goo would be used to create 3D chip packages, which still use off-chip signaling to communicate up and down the stack, or 3D integrated circuits, which have connections on adjacent chips that allows on-chip signals to flow up and down the stack at silicon speeds and voltages.
Obviously, the latter is more useful than the former, but it would probably be best to perfect the adhesives on separate components – a few processors and some memory in a stack connecting off chip – than a complete system on a stack.
It also seems likely that IBM wants to bond whole wafers together, test the connections on all the processing elements, and then cut them up into individual towers for separate devices such as a smartphone or gaming console. Aligning a set of 300mm wafers once is a lot easier, and much more cost-effective, than aligning a hundred smaller sets of chips individually.
One more benefit of the 3D chip stack is that different layers of circuits can be implemented in different processes, with the best and cheapest process used for each component, unlike a 2D system-on-chip, which has to implement all circuits in the same process. ®
I really wish I could skip the title - I can never think of anything witty
I am, I think, gobsmacked
Part of me is going "ooo... that's so cool!"
Part of me is going "what took them so long to think of this?"
And the rest of me is wishing I'd thought of it.
So I'm just gonna go with "damn that's cool"
Titles aren't that important.
What I think Pooka isn't to much that nobody had thought of it before. But making the architecure and adhesive is what's so tough.
It will certainly be a better patent then apple's Ipad design. I approve of this.
Don't forget that most (genuine) enterprise kit already has lots of redundancy tricks built in to cope with broken memory (or even processors for that matter). Same way as disks actually have a whack of spare capacity above their stated amount to allow for bad block relocation. They can just build spare capacity in the stack...
When did you last have to replace a CPU or a DIMM?
Silicon chips are amazingly reliable. I see a DIMM that failed in service once or twice a year (8 or 16 chips per DIMM, 2 or 4 DIMMs per PC, about 400 PCs). And I suspect most of those failures are with the soldered joints onto the PCB, or with the connector.
I've seen a failed CPU twice in twenty-plus years. (Maybe a few of the old boxes that went straight to the scrap-heap were CPU failures rather than MoBo failures, but either way they'd lasted well into obsolescence).
At this level of reliability, a stack of 100 will still be acceptably reliable. Possibly, more so than the same 100 chips soldered onto a board (which you don't repair anyway in most cases).
Tiny holes and cables
Several companies including Intel and IBM are working on this concept of 3D silicon skyscrapers.
Puting multiple layers in the same package (what many including Apple) have done, is nothing (and very different from) compared to 3D chips.
In 3D chips, many tiny holes are 'drilled' in the silicon material through which the cabling goes from layer to layer. These 'holes' and 'cables' are microscopic. I believe somewhere in the range of Microns, but it might as well be much smaller.