OCZ samples twin-core ARM SSD controller
Do you need a bit of TLC?
OCZ is sampling a new flash controller that gives a picture of future solid state drives.
The company bought Indilinx for its solid state drive (SSD) controller technology in March this year and has now unveiled the Indilinx Everest controller platform.
It has a 6Gbit/s SATA III interface, a dual-core ARM processor and a number of enticing features, such as 3-bit multi-level cell (MLC) support. This is going to be called TLC, for triple-level cell, to distinguish it from today's MLC, which is 2-bit MLC.
OCZ said the platform will support flash process geometries down to the 19-10nm range (1x). Today we have flash in the 39-30nm range (3x) which is transitioning to 29-20nm (2X). With each downwards jump the number of flash dies on a wafer increases and the cost/die shrinks.
OCZ says Everest supports up to 200 mega-transfers/sec whereas today's controllers, such as the Sandforce ones used by OCZ, support up to 166MT/sec or so. The device also supports 1TB capacity SSDs and has an 8-channel design with 16-way interleaving that supports ONFI 2.0 and Toggle 1.0. This will provide sequential bandwidth up to 500MB/sec.
There is a 400MHz DDR3 DRAM cache facility that can support up to 512MB of such cache. The controller is optimised for 8K writes – which matches, the 8K page size typical of the latest flash, OCZ says.
SSDs powered by this controller can have their boot time cut in half compared to today's controllers because of OCZ's boot-reduction time algorithms. This, OCZ says, will support "instant on" requirements.
It supports TRIM, SMART, NCQ with a queue depth of 32, 70-bit ECC, and many over-provisioning options to extend the SSD's working life. It also has OCZ proprietary Ndurance technology to extend flash's working life.
OCZ says it is available for evaluation now by OEMs and, we presume, OCZ will be using it in its own flash products. We're looking at 1TB SSDs using TLC flash, shipping sequential data out at 500MB/sec which boot quickly, and could be combined to provide multi-TB flash data stores. Parallelising data access would provide multi-GB/sec I/O. The flash future looks bright. ®
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