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ARM daddy simulates human brain with million-chip super

RISC chip choice is a no-brainer

Internet Security Threat Report 2014

ARM choice is a no-brainer

Figuring out how the brain works is tough, and the processor and communication network design for the SpiNNaker system is easy by comparison.

It was a no-brainer that Furber, who designed the 32-bit ARM processor while at Acorn, would opt for an embedded variant of that chip for the SpiNNaker system. Not just because of his familiarity with the processor architecture and the wide variety of tools and expertise in customizing the ARM processors, but because of the energy efficiency inherent in the ARM design.

"Embedded processors can reduce the capital and energy costs of a given level of compute power by about an order of magnitude, thereby significantly reducing the ownership (and environmental) costs," Furber and Brown write. "The embedded processor technology employed in SpiNNaker delivers a similar performance to a PC from each 20-processor node, for a component cost of around $20 and a power consumption under 1 watt."

So far the SpiNNaker team has designed processors with four and eight ARM968E-S cores, and run them through the simulator, and is pretty confident that it can crank the design up to 20 cores on a single die. In each set of 20 cores, one of the cores is designated as a monitor processor, a kind of head node for the SoC that controls how code is loaded on the remaining 19 cores, which will run the neural network simulation. Each ARM968E-S core will has 64KB of data cache and 32KB of instruction cache, a communications controller that simulates neural spikes using packets, and a memory controller to link to 1GB of DDR1 main memory (yes, DDR1, people) that is in the chip package but not on the die.

SpiNNaker ARM system on chip

The SpiNNaker ARM-based system on chip (click to enlarge)

The communications network-on-chip (NoC) device was created by Silistix, a company that Furber created and spun out of the UofM. On the die itself, there is an on-chip interconnect that allows the ARM cores to access memory, networking ports, and other shared resources. The design embodies what Furber and Brown call a Globally Asynchronous Locally Synchronous (GALS) architecture, which again doesn't mean thinking about sex at all.

SpiNNaker 2D mesh interconnect

SpiNNaker's 2D mesh interconnect

What it does mean is that the simulated neurons can fire off a pulse to any other simulated neuron in the million-core system in about 1 millisecond, which just so happens to be about as fast as your neurons do it. The resulting interconnect fabric links the cores together in a 2D mesh network, which can be used to model 3D brain structures. 2D mesh networks are common in massively parallel supercomputers, although they are certainly not the only way to lash machines together.

Neither Furber nor Brown think that the SpiNNaker machine will help solve the wetware riddle of the human brain. But they think that a million-ARM machine will go a long way towards helping researchers run better models of the brain on a system that acts more like the human brain than previous hardware did.

Funding for the SpiNNaker project is being provided by the UK Engineering and Physical Sciences Research Council through the universities of Southampton, Cambridge and Sheffield. ARM, Silistix and military contractor Thales are also kicking in support.

Of course, to simulate 90 billion neurons (with some spares in the box) will take something on the order of 100 times more cores than the SpiNNaker system will have. If Moore's New Law – the number of cores on a chip doubles every 18 months – can hold for the next 25 years, then we'll be at a million cores or so per chip. So a hundred of those puppies – call it a rack – should be able to simulate a human brain. And here's the funny bit. Even if that does happen, and let's say it consumes 25 kilowatts to be generous, the human brain will do it at around 20 watts. Nature will still be winning. ®

Internet Security Threat Report 2014

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