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Caswell crams MIPS chips into cloud crates

Micro servers aren't just for Xeons, Atoms

Internet Security Threat Report 2014

Taiwanese network and communications equipment manufacturer Caswell has thrown its hat into the micro-server ring – but instead of starting out with a box based on x64 processors from Intel or AMD, the box maker is adopting a variant of the MIPS RISC processor.

At this week's Computex trade show in Taipei, Caswell and chip partner Cavium Networks showed off the CCS-3400 and CCS-3300 "micro-motherboard blade server", which is what you and I would call a micro server since the machines don't have integrated switches and a common networking backplane in a single chassis. However, that definition is a bit fuzzy since Caswell is also making available an in-chassis switching module for Gigabit Ethernet and 10 Gigabit Ethernet networks.

Caswell Cavium micro server

Caswell's MIPS-based micro server

Cavium Networks has a line of MIPS-derived processors called Octeon, which implement the MIPS64 architecture and span from 2 to 64 cores on a single die. There are a number of different Octeon processors, used in firewalls, intrusion detection and prevention, and other kinds of network devices, as well as in storage arrays for storage controllers.

For their micro servers, Caswell chose the dual-core Octeon Plus CN5020, a dual-core MIPS chip designed for broadband gateways and other embedded network devices, with TCP acceleration, encryption, and network quality-of-service features scratched onto the chip.

Each MIPS64 r2 core on the Octeon Plus CN5020 has 32KB of instruction cache, 16KB of data cache, and a 2KB write buffer, plus packet processing and security coprocessors embedded on the chip. The coherent interconnect implemented in the Octeon architecture links the cores and their memories to each other, and to 128KB of shared L2 cache memory and a hyper access memory controller that links out to DDR2 memory sticks in the server.

The individual server nodes implemented on the trays support 400MHz, 533MHz, and 667MHz DDR2 SODIMM modules with a maximum capacity of 1GB. This might seem a bit skinny for a lot of workloads, but it's fine for many jobs.

Each node has a CF socket for peripheral expansion and one SATA port to link out to an external SATA switch module that in turn can be used to link to external storage arrays. Each node has two Gigabit Ethernet interfaces, which can link to external switches at the top of the rack or to the internal switches at the back of the chassis.

The Caswell micro server puts ten of these Octeon Plus CN5020 processors onto a single tray, for a total of 20 cores per micro server. The CCS-3300 chassis has redundant 1,600 watt power supplies, and can put eight of these trays in a 4U chassis for 160 cores total, while the CCS-3400 chassis puts redundant 2,000 watt power supplies in an external 1U unit chassis (mounted in the back of the server rack) and allows customers to put ten trays into the 4U chassis, for 200 cores maximum. You can get ten of these enclosures in a rack, for a total of 1,600 or 2,000 cores per rack. Caswell says the resulting machine consumes about 15 watts per core when running workloads.

If customers want integrated storage – be it disk drives or SSDs – they can swap out two of the Octeon motherboards and plunk in a 3.5-inch storage device of their choice, and use the SATA switch to link the remaining server nodes to this storage. The leanest CPU and heaviest storage configuration on the micro server tray comes with four processors (for a total of eight MIPS cores) and three storage devices on the tray.

Caswell is cooking up a variant of this micro server that will use Intel's Atom E660T, but it's not clear when it will be available. The MIPS variants of the machines are available now; pricing information was not available at press time.

The Caswell machines support MontaVista's real-time Linux variant as well as Intel's Wind River VxWorks and ENEA's OSE, both of which are also real-time operating systems and generally support embedded processors based on ARM, Power, and MIPS architectures. ®

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