Intel outs 'Poulson' speeds and feeds
Yes, more chip porn!
ISSCC Intel has released some additional about its future eight-core "Poulson" Itanium processors.
The Poulson chips are the first Itaniums to have a new microarchitecture and core redesign since the "McKinley" cores a decade ago. As previously reported, the processor has a total of 3.1 billion transistors and is implemented in Intel's current 32 nanometer wafer baking technologies, which includes strained silicon.
The Poulson chip is 18.2 by 29.9 millimeters (544 square millimeters) and has about 20 per cent less die area than the quad-core "Tukwila" Itanium 9300 chip it will eventually replace in the lineup probably in early 2012 if Intel can stick to the two-year cadence is it trying to set for the Itaniums so Hewlett-Packard, the last big user of the Itanium chips, can keep pace with Power and Sparc upgrades.
El Reg was missing a whole bunch of information about the Poulson chip when Intel gave prebriefings ahead of the ISSCC event, but Reid Riedlinger, the chief chip engineer for the processor, filled in some gaps in his presentation at ISCCC. For one thing, Riedlinger's presentation had die shots that showed a lot of the salient features of the processor, which Intel did not provide in its briefings to the press.
So, here is what the Poulson chip looks like:
Like the future "Sandy Bridge-EP" and "Westmere-EX" Xeon processors from Intel, which El Reg told you all about here from ISSCC, the Poulson Itanium chip is a "cores-out" design, which means that the cores are on the outside of the chip with the shared L3 caches occupying the center of the chip.
The QuickPath Interconnect (QPI), which allows point-to-point communication between processors in adjacent sockets in a system board and across multiple systems boards in an SMP server, run along the top, and the Scalable Memory Interconnect (SMI) DDR3 memory controllers and buses run along the bottom. Here's a slightly better Poulson chip schematic than Intel was handing out in its prebriefs:
Riedlinger gave out the transistor budget for the Poulson chip, which was interesting. About 712 million of those transistors are for the cores themselves, with the remaining 2.44 billion going for the uncore portions. Most of that is, as you can see from the chip shot, used up in the shared L3 cache, which is segmented in 4 MB blocks (one per core) and linked together by a high-speed, bi-directional ring interconnect.
Riedlinger said that the core logic's 712 million transitors took up about 158 square millimeters of area, ran at between 0.85 and 1.2 volts, and burns about 95 watts. The L3 caches had 2.17 billion transistors, ran at between 0.9 and 1`.1 volts, but only burned 5 watts; the L3 caches occupied 163 square millimeters of chip real estate. The system interconnect circuits linking the cores to the L3 caches on the chip were fashioned from 22 million transistors, ate up 137 square millimeters of space, ran at the same 0.9 to 1.1 volts, but burned 50 watts. The I/O logic (QPI, memory controllers, and SMI buses) were etched with the final 44 million transistors, ate 68 square millimeters of chip area, ran at 1.05 to 1.1 voltage, and slurped 20 watts under load.
The Poulson chip has a total of 54 MB of SRAM memory on it. This includes 32 MB of L3 cache, 2 MB of total L2 data cache, 4 MB of total L2 instruction cache, 2.2 MB of director cache, 3.6 MB of last level tags, and a tiny slice (169 KB) of L2 instruction tags. Don't forget the L1 data and instruction caches on each core.
Next page: The funny bit
They'll make a return even if they don't sell a single chip
This processor is the "anti-core" meaning that the majority of the design is based on making things like faster cache, faster interconnects, faster instructions etc... unlike the Core series of processors which really shine because of the huge amount of real estate allocated to instruction reordering and interpretation.
With this chip, Intel developed new power plane technologies, they developed new core communication technologies, they developed new cache sharing tech etc.... additionally, they figured out how to provide and manage a bunch of multiple API. Also, it appears their SMP methodology is relatively new for them.
Let me draw attention to the fact that as opposed to sucking a bunch of technology from the Core platform, they developed most of the new goodies in these chips FOR these chips. So, in reality, it's a huge test bed for all the good things to come in the Core series of chips in later generations. By bring what they learned here to the Core chips, they should be able to provide more cores, faster buses, more optimal instructions and such.
So, just the IP generated from this project which will be the groundwork for later Core and Xeon chips is more than enough ROI. What they make selling these actual chips is probably just gravy :)
But will they ever sell enough to get a return?
Still only 5 QPI links...and will be as long as they keep the same socket
"The one funny bit in the Poulson design are the two half-QPI links at the bottom of the chip. These were added, accoording to Riedlinger, to provide glueless interconnections for eight-socket machines. Iit would not be surprising to see them used as interconnects for linking even larger systems into a single SMP image with a modified "Boxboro" chipset from Intel or a tweaked sx3000 chipset from HP, which is used in its Integrity Superdome 2 servers."
Very strange statement as the current chip Tukwila also has the two 1/2 QPI links which add up to 1 QPI link for a total of 5. If you do the math 1 QPI link for I/O, 4 QPI links to talk to other chips then you get direct connect to 5 chips not 8. Yes it's glueless, but CPU0 has to go thru CPU6 to get to CPU7. Just look at HP's 4 wide blade wire diagram. It's borderline design flaw, but they choose not to put in the SX3000 chipset into the blades.
The Superdome2 and the SX3000 chipset is even more interesting as it only uses 3 of the QPI links as the other two are wasted.
I did not see the chip speed here but it will be 2.4GHz
Re: Odd choice of name...
I was thinking more of Meat Loaf
Odd choice of name...