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Intel outs future Xeon chip porn

Get a load of them cores!

Application security programs and practises

Mystery 32nm silicon

Shenggao Li, a chip engineer from the Santa Clara team, gave a presentation on clock generation for a "32nm server processor with scalable cores" that no doubt is the future Sandy Bridge-EP Xeon processor for two-socket servers.

Here's what the chip actually looks like:

Intel Sandy Bridge Xeon

And here is what the block diagram for the chip looks like:

Intel Sandy Bridge Xeon Block Diagram

Like the future Westmere-EX Xeon and Poulson Itanium, this future Sandy Bridge-EP processor has a "core-out" design that puts the shared L3 caches in the center. Like the Westmere-EX, the Sandy Bridge-EP chip has a dozen ring stops on this internal cache interconnect, even though it only has eight processor cores. You can see the extra two L3 cache segments at the top and bottom of the central cache, and each of those segments have two ring stops instead of one.

This implies that the Sandy Bridge-EP is actually designed to scale to a dozen cores, which Intel will be able to do by stretching the caches out and adding cores to the ring. The scissors on the right side of the block diagram near the word "Scalability" implies this, but Li never said Intel intended to ramp the core count on this Xeon to a dozen cores. But clearly the chip maker can do so if Advanced Micro Devices starts winning the Core Wars among x64 server buyers.

The Sandy Bridge-EP chips have QPI buses in top of the chip. Intel has not said how many, but the same two as the prior Xeon 5500 and 5600 processors seems almost certain, and very likely running at the same peak 6.4 GT/sec speed. The chip has an integrated PCI-Express peripheral controller on top and two DDR3 main memory controllers at the bottom.

Intel did not provide a shot of the Sandy Bridge-EP chip package, but Li said that the die will measure around 20 by 20 millimeters and will be packed with 2.2 billion transistors. ®

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