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Chip upstart Tilera lines up $45m in funding

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Taking a peek under the hood

Each core on the Tile-Gx chips has 32 KB of data and instruction cache and 256 KB of L2 cache; those L2 caches are turned into a 26 MB virtual L3 cache. The Tile-Gx chips also have additional SIMD instructions that make use of a four multiplier-accumulator (MAC) per cycle unit that can deliver 600 billion MACs per second, which Tilera says is 12 times the fastest digital signal processor on the market today. The chips also spore two MiCA engines (short for Multistream iMesh Crypto Accelerator), which are able to deliver 40 Gb/sec of bandwidth on cryptographic work and 20 Gb/sec on compression and decompression. The chip also includes a packet-processing accelerator, which sits between the cores and the on-chip network interfaces, called mPIPE (multicore programmable intelligent packet engine), which does load-balancing between the cores and the network interfaces.

Tilera's TileGx processors run Linux and the same Apache-MySQL-PHP-Python stack that a lot of cloud providers rely on. More importantly, Tilera has created a tool called the Multicore Development Environment that includes a standard Linux 2.6 SMP implementation for the cores plus C and C++ compilers, a hypervisor for hardware abstraction and virtualization, a graphical tool for debugging multicore applications, and an Eclipse plug-in.

Tilera has 85 people now, and is of course fabless – as any sane young chip company has to be these days. Bailey says that Tilera will be using the money from the fourth funding round to beef up its sales operations as well as speeding up its development. While the plan has not been hammered out yet, one option is to bring on a second design team that can do the testing and qualification work on the current TileGx chips, so that the current team can work on the future Stratton chips. Another option is to add people to create some custom derivatives of the TileGx chips that might be of interest to current and potential customers.

Incidentally, Tilera was only seeking about half as much money as it received in its fourth round, according to Bailey. So it boosted the number and that was quickly oversubscribed. It looks like there is a bit of enthusiasm over the possibility of mobile computing and cloud computing giving different chip architectures like ARM and Tilera a chance to compete against Intel and Advanced Micro Devices. And why not? Chewing up from the bottom is how the x64 architecture killed off myriad processors used in proprietary and RISC systems, after all.

One last thing: Bailey confirmed that the top-end "Stratton" part could be a 15x15 grid with 225 cores. Prior to today, the company was saying it would have 200 cores, which obviously cannot make a square. (You could do 14x14 to get 196 cores.)

So is the Tilera IPO scheduled to coincide with the Stratton chips? Stay tuned... ®

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