Oracle revisits Sparc T processor roadmap
Time to overclock, boys
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Three weeks ago, Oracle co-founder and chief executive officer, Larry Ellison, gave us all a preview of the upcoming Sparc T series processor roadmap as part of the rollout of the Sparc SuperCluster, an Exadata-style parallel database machine based on the current Sparc T3 processors. In the wake of Ellison's revelations, Rick Hetherington, vice president of hardware development at Oracle, did a Q&A interview with Oracle PR that shed a little more light on the Sparc T chip roadmap.
In that Q&A interview, which you can see here, Hetherington said that the next-generation Sparc T4 processor was "less than 12 months away," and said that Oracle had over 1,000 engineers working on the processors. Hetherington added that the Sparc T4 had a new core that "brings together the combination of throughput performance through threading as well as really high-speed single thread performance" and said further that this core was developed in 2006 and 2007 and would be delivered in 2011.
Take a look at the Sparc processor roadmap from circa June 2009, which Sun was showing to customers in the wake of killing off the 16-core "Rock" UltraSparc-RK processor:
The Sparc roadmap, post Rock and hard place (click to enlarge)
The current "Rainbow Falls" Sparc T3 chip, which has 16 cores with eight threads in each core, runs at 1.65 GHz and is implemented in a 40 nanometer process by Sun and now Oracle wafer baking partner Taiwan Semiconductor Manufacturing Corp. There was supposed to be a 2.5 GHz, 40 nanometer part coming out in 2011 on the original Sun roadmap, called "Yosemite Falls," due in late 2011 and then a pair of 3 GHz chips with either four or 16 cores, called "Yellowstone Falls" and "Cascade Falls," due in 2012. Yosemite Falls, Yellowstone Falls, and Cascade Falls were all to use a new core, code-named VT.
Now take a look at the current Ellisonized Sparc roadmap:
Oracle Sparc processor and system roadmap (click to enlarge)
Oracle has been promising a 3X improvement in "single strand" performance, which everyone takes to mean clock speed. Being rambunctious and eager to see Oracle compete with IBM and Intel in the chip racket - in a way that Sun used to - I assumed that the Oracle Sparc roadmap implied a factor of 3X boost in clock speeds over the current Sparc T3 chips, not over the low-bin 1 GHz clocks on the original Sparc T1 chips from 2006. But if you assume that Oracle means the latter and not the former, then the Sparc T4 could come in at a mere 3 GHz, not the 4.8 GHz to 5 GHz I had been hoping for based on comparisons to the current generation of Sparc T2+ and T3 chips.
What it looks like to me is that Oracle is taking the Yosemite Falls processor from the original Sun Sparc roadmap and cranking it up to the Yellowstone Falls speed.
Hetherington also said in the Q&A interview that the Sparc T5 would have 16 cores like the current Sparc T3 chip does, and said further that the T5 chip would be implemented in a 28 nanometer process. That seems to mean to me that Oracle has killed off Yellowstone Falls and the Sparc T5 is actually Cascade Falls, more or less.
In the future Sparc T family of chips, explained Hetherington, Oracle will be aligning its application, database, and middleware stack to the Sparc chips and vice versa such that when performance is critical for instructions relating to an Oracle application, one thread on a multithreaded core in a Sparc T machine can hog the thread and not share resources with other threads, allowing the application to run faster. Lower priority applications get threads when they become available. Hetherington did not elaborate on how much extra performance at the system level this might yield.
IBM does a similar thing with the four threads on each core of the Power7 processors, by the way, which it calls intelligent threading.
One last thing: In the story on the Sparc T4 and T5 chips from three weeks ago, I suggested that Oracle might be overclocking the Sparc chips to reach the 5 GHz stratosphere of chip clock speeds. While this might not be the case, the question we need to be asking Oracle - and remember, Oracle doesn't answer questions - is: if not, why not? For a certain set of customers, particularly in the financial services segment that Sun used to utterly dominate, a hot server is not nearly as bad as one with a low clock speed.
Maybe there is a place for overclocked Sparc T4 and T5 machines, which come with a premium price and which need to have their processors replaced perhaps once a year. So searching through the Sparc bins to find parts that can run at maybe 4 GHz and then putting advanced cooling such as water blocks on the chips to keep them cool would make Oracle's lineup more competitive with the Unix systems from IBM and Hewlett-Packard and keep better pace with high-end Xeon boxes from Intel's server partners.
It isn't the dumbest idea out there. Appro International and Silicon Graphics are starting to sell overclocked Xeon servers. So what is wrong with Oracle selling overclocked Sparc T servers? ®
COMMENTS
Not over clock
Oracle is not going to over clock to get 3x better thread performance.
I talked to the chief architect of T4, and he said that the T4 cores are redesigned. Earler, Niagara cores have basically been the same: simple with no OO order execution, etc. Now, for the first time, T4 will have a totally redesigned and much beefier core with OO-order execution, etc.
So the 3x better thread performance comes from a beefy core. It is not the same simple cores, with much higher cpu Hz. It is a new beefy core.
re: RE: re: So ...
It was just a joke. Yes, I know you guys on opposite sides of the discussion when it comes to Itanic and Power, but your tired fud when it comes to SPARC is overly repetitive.
The fact is, Sun stated that they designed the "beefy" cores 5 years ago, and are just now getting them out to market. That does not sound like a change in direction, it sounds like clear planning. Increase the thread count, then make those same threads faster once the technology can handle it.
Not a change, just a natural progression.
RE: Isn't T3 already cache/memory starved?
Some processor architectures are impacted more than others with a small cache.
SPARC T processors are not always pushing registers to memory when there is a miss. Each thread can stall in it's place and continue once the data is available. The availability of many threads keep the CPU cores always busy on a loaded system. Also, SPARC utilized windowed registers, reducing the need to push registers to memory. Also, the bus passing between the CPU and memory is usually a really high capacity on the T systems.
Other processor architectures don't have the ability to reduce register pushes to slow memory. Also, when a thread of execution stalls on other architectures, it is normally very expensive since the CPU core remains idle. Other architectures use larger caches to keep the CPU pipelines full and processing, often to compensate for low memory bandwidth on the bus going from a CPU.
Since the SPARC T processors are not impacted as greatly by cache size as much as with other architectures, cache is not a relevant apple-per-apple metric when comparing to other architectures. It was a design decision to leverage the transistors in the die to add additional threads in order to keep the cores more busy instead of adding additional cache to keep the cores less busy.
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