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'Wear levelling' - a bedroom aid for multi-layer cell Flash

Helps it last longer

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TRIM

It is harder for SSDs used in business and desktop computing applications as a large number of small writes can occur, ones of 4KB or less with Windows, according to a SanDisk spokesperson, Don Barnetson. Host operating systems could manage SSD storage better, by batching up small writes or suchlike, and some SSD controllers do that by caching writes until a large amount of data to be written has built up.

However, host operating systems for notebooks, desktops and servers assume their online storage outside main memory is disk and write to what they think are disk devices. The SSD controller simply has to cope.

One way that operating systems have improved is with the TRIM command. This command is used by operating systems like Windows to tell the SDD controller that certain sets of data are no longer valid. Normally an O/S file system tracks which files are valid or deleted.

If a file is deleted the file system sends a note to itself saying certain disk sectors are now available for use again. It does not tell the hard disk drive controller that though; there is no need. So, up until the TRIM command came along it didn't tell the SSD controller either.

When TRIM is supported then the SSD controller can can then work out the flash blocks involved when a disk sector holds invalid data - it already maps disk sectors to flash blocks as part of its day job as it were - and add them to the background garbage collection pool. This way it can build up a buffer of free blocks that can be written to far more quickly than if an entire read-erase-modify-write cycle were needed for a block.

Signal processing

Flash cells don't simply stop working when they have received one write request more than they can manage. Instead the quality of information they return to a read request degrades over time until the flash controller can no longer use it. Israeli startup Anobit is using software digital signal processing (DSP) technology to better extract a flash cell's information from what channel processing people call noise.

There is a signal to noise ratio (SNR) for the channel to a flash cell and Anobit says its DSP algorithms can extract the signal at lower signal to noise ratio levels than existing hardware methods. As the cells' signal to noise ratio has more of a noise component due to the write-erase cycles mounting up, Anobit says its controllers can continue to use the NAND chips long after other controllers have given up.

It claims it can produce 2-bit MLC flash drives supporting 50,000 write/erase cycles, five times more than the Samsung number above. This is with its first generation technology. Anobit says its product has a five-year endurance for its 200GB SSD with a 2TB/day write rate and a 10-year endurance for its 400GB product at the same rate, or five years at 4TB/day.

It calculates this by multiplying the capacity of the SDD by ten, then by the number of days in a year, then by five for five years, and then by a 2.7 write amplification factor. Each cell in the SSD is written to 10 x 365 x 5 x 2.7 = 50,000 times or cycles.

Anobit reckons its second generation product will support up to 100,000 cycles for 3-bit MLC using sub-20nm process technologies. Data reading takes longer this way than using pure hardware to read the flash, but Anobit suggests reading multiple pages in one read event could compensate for that.

If these claims are justified then DSP could become a standard part of a flash controller's technology. It's interesting to note that STEC's latest CellCare technology uses signal processing as well as data management algorithms to improve MLC endurance.

The promise of MLC

The great promise of MLC flash is that it will make flash affordable, engendering much wider use. But this is only the case if it has an acceptable working life.

Its endurance is being extended wear-levelling methods, over-provisioning (which unfortunately adds to its cost), TRIM support and signal processing. Of course there are other necessary factors such as a low error rate, but that is not the focus of this article.

The net of all this is that each flash cell should be written to the same number of times as its neighbour as far as possible, and the overall number of writes minimised by better organising the SSD's resources and tracking of cell, page and NAND block status.

Lastly, DSP techniques promise to dramatically increase cell content readability as wear levels go up. ®

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